Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress

This work investigates an improvement in anomalous on-current and subthreshold swing (SS) in Low-temperature polycrystalline-silicon thin-film transistors after positive gate bias stress. The experimental results reveal that the improved electric properties are due to the hole trapping at $SiO2$ above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the SS. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above.