Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform proof-of-concept simulations of junctionless gated Si nanowire transistors. Based on first-principles, our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of wire diameter and gate length, and that the junctionless transistor avoids potentially serious difficulties affecting junctioned channels at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.
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We validated this by using but introducing a uniform energy shift to the NEGF Hamiltonian in the gated region. This neglects capacitance and screening in the oxide and SiNW but enables us to quantify the tunneling current through the channel.
© 2010 American Institute of Physics.
2010
American Institute of Physics
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