A side-gated ultranarrow channel (width <10nm) silicon field effect transistor (FET) with extreme threshold voltage (Vt) tunability is described. A narrow inversion layer is formed on the top interface controlled by the top gate. The device body and side interfaces are accumulated by up to 1019cm3 holes, drawn from the substrate by negatively biased side gates (Vside), increasing Vt by 3V, suppressing peripheral leakage currents and short channel effects. Vt response to Vside follows a square root behavior, dVtdVside=3.73VV, similar to that of body doping. Maximum linear tunability (dVtdVside) exceeds 2VV, average dVtdVside is 1.67VV.

1.
D. M.
Fried
,
J. S.
Duster
, and
K. T.
Kornegay
,
IEEE Electron Device Lett.
24
,
592
(
2003
).
2.
Y. X.
Liu
,
M.
Masahara
,
K.
Ishii
,
T.
Sekigawa
,
H.
Takashima
,
H.
Yamauchi
, and
E.
Suzuki
,
IEEE Electron Device Lett.
25
,
510
(
2004
).
3.
D. J.
Frank
,
IBM J. Res. Dev.
46
,
235
(
2002
).
4.
A.
Gokirmak
and
S.
Tiwari
,
Electron. Lett.
41
,
157
(
2005
).
5.
A.
Gokirmak
and
S.
Tiwari
,
MRS Symposia Proceedings No. 833
(
Materials Research Society
,
Pittsburgh
,
2005
), p.
G6
9
.
6.
A.
Gokirmak
, Ph.D. thesis,
Cornell University
,
2005
.
7.
P.
Sallagoity
,
M.
Ada-Hanifi
, and
M.
Paoli
,
M.
Haond
,
IEEE Trans. Electron Devices
43
,
1900
(
1996
).
8.
A. K.
Roy
,
S.
Mukhopadhyay
, and
H.
Mahmoodi-Meimand
,
Proc. IEEE
91
,
305
(
2003
).
9.
A.
Czerwinski
,
E.
Simoen
,
A.
Poyai
, and
C.
Calaeys
,
J. Appl. Phys.
88
,
6506
(
2000
).
10.
G.
Verzellesi
,
G. F. D.
Betta
,
L.
Bosisio
,
M.
Boscardin
,
G. U.
Pignatel
, and
G.
Soncini
,
IEEE Trans. Electron Devices
46
,
817
(
1999
).
11.
Y.
Taur
and
T. H.
Ning
,
Fundamentals of Modern VLSI Devices
(
Cambridge University Press
,
Cambridge, UK
,
1998
), p.
99
.
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