Effects of gate edge profile on off-state leakage suppresion in metal gate/high-$k$ dielectric $n$-type metal-oxide-semiconductor field effect transistors

The impact of process integration on device characteristics of metal gate/high-$k$ device was investigated systematically. It was found that the profile of gate stack edge and following processes should be optimized to achieve low gate-induced drain leakage, gate leakage, and high drive current. For low standby power applications, an offset of high-$k$ dielectric layer was more desirable. With an optimized gate edge profile, the authors achieved 100 times lower off-state current compared to previous reported results. However, the saturation current degradation was minimal.