Vertical surround-gated silicon nanowire impact ionization field-effect transistors

One of the fundamental limits in the scaling of metal oxide semiconductor field-effect transistor technology is the room-temperature (RT) limit of $∼60mV$/decade in the inverse subthreshold slope. Here, the authors demonstrate vertical integration of a single surround-gated silicon nanowire field-effect transistor with an inverse subthreshold slope as low as $6mV$/decade at RT that spans four orders of magnitude in current. Operation of the device is based on avalanche breakdown in a partially gated vertical nanowire, epitaxially grown using the vapor-liquid-solid method. Low-power logic based on impact ionization field-effect transistors in combination with a vertical architecture is very promising for future high-performance ultrahigh-density circuits.