Reported here is the fabrication of channel length pentacene field-effect transistors (FETs) with well-behaved current-voltage characteristics. Using a solution deposition method, pentacene grains span entire devices, providing superior contacts. Varying the gate oxide thickness, the effects of scaling on transistor performance is studied. When the channel length to oxide thickness exceeds 5:1, electrostatically well-scaled nanometer FETs are prepared. The results show that the device characteristics are dominated by the contacts. Decreasing the oxide thickness lowers the device turn-on voltage beyond simple field scaling, as sharper bending of the gate potential lines around the contacts more effectively reduces the molecule/source interfacial resistance.
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30 October 2006
Research Article|
October 30 2006
Device scaling in sub- pentacene field-effect transistors
G. S. Tulevski;
G. S. Tulevski
Department of Chemistry,
Columbia University
, New York, New York 10027 and the Columbia University Center for Electronics of Molecular Nanostructures, Columbia University
, New York, New York 10027
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C. Nuckolls;
C. Nuckolls
Department of Chemistry,
Columbia University
, New York, New York 10027 and the Columbia University Center for Electronics of Molecular Nanostructures, Columbia University
, New York, New York 10027
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A. Afzali;
A. Afzali
IBM T. J. Watson Research Center
, Yorktown Heights, New York 10598
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T. O. Graham;
T. O. Graham
IBM T. J. Watson Research Center
, Yorktown Heights, New York 10598
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C. R. Kagan
C. R. Kagan
a)
IBM T. J. Watson Research Center
, Yorktown Heights, New York 10598
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a)
Electronic mail: [email protected]
Appl. Phys. Lett. 89, 183101 (2006)
Article history
Received:
May 11 2006
Accepted:
September 04 2006
Citation
G. S. Tulevski, C. Nuckolls, A. Afzali, T. O. Graham, C. R. Kagan; Device scaling in sub- pentacene field-effect transistors. Appl. Phys. Lett. 30 October 2006; 89 (18): 183101. https://doi.org/10.1063/1.2364154
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