Field-effect transistors on rubrene single crystals with parylene gate insulator

I. H.

Campbell

and

D. L.

Smith

, , ().

A. R.

Brown

,

C. P.

Jarrett

,

D. M.

de Leeuw

, and

M.

Matters

, , ().

G.

Horowitz

, , ().

S. F.

Nelson

,

Y.-Y.

Lin

,

D. J.

Gundlach

, and

T. N.

Jackson

, , ().

N.

 

Karl

,

K.-H.

 

Kraft

,

J.

 

Marktanner

,

M.

 

Münch

,

F.

 

Schatz

,

R.

 

Stehle

, and

H.-M.

 

Uhde

,  , ();

W.

Warta

and

N.

Karl

, , ().

G.

Horowitz

,

M.

Hajlaoui

, and

R.

Hajlaoui

, , ().

C.

Kloc

,

P. G.

Simpkins

,

T.

Siegrist

, and

R. A.

Laudise

, , ().

Prior to the FET fabrication, the purity of the crystals was tested by studying the transport properties of the intrinsic (bulk) carriers. We measured the current between two thin-film contacts deposited at the crystal surface as a function of the applied voltage. The crossover between the ohmic and the space-charge-limited current regimes [K. C. Kao and W. Hwang, Electrical Transport in Solids (Pergamon, Oxford, 1981)] has been observed at relatively low voltages. For some samples, we have observed the transition to the trap filling regime at much higher voltages. These results, which will be published elsewhere, indicate that the bulk concentration of traps in the rubrene crystals is relatively low $(Nt∼1017 cm−3),$ and the carrier injection from thin-film Ag contacts into the bulk occurs at low bias voltages.

The parylene coatings are widely used in the packaging applications; the deposition equipment for parylene is inexpensive and easy to build (see, e.g., Parylene Conformal Coatings Specifications and Properties, Technical notes, Specialties Coating Systems).

E. J.

Meijer

,

C.

Tanase

,

P. W. M.

Blom

,

E.

van Veenendaal

,

B.-H.

Huisman

,

D. M.

de Leeuw

, and

T. M.

Klapwijk

, , ().

S. M. Sze, Physics of Semiconductor Devices (Wiley, New York, 1981).

The resistance of the Schottky barriers at a metalorganics interface could be very large, especially at low temperatures.

Application of a positive bias to the source electrode with respect to the drain electrode induces a negative “image” charge at the gate electrode. For a thresholdless transistor, this results in a formation of a conducting channel even at $Vg=0.$ To pinchoff the channel, a positive gate voltage should be applied.