Relaxed SiGe attracted much interest due to the applications for strained Si/SiGe high electron mobility transistor, metal-oxide-semiconductor field-effect transistor, heterojunction bipolar transistor, and other devices. High-quality relaxed SiGe templates, especially those with a low threading dislocation density and smooth surface, are critical for device performance. In this work, SiGe films on low-temperature Si buffer layers were grown by solid-source molecular-beam epitaxy and characterized by atomic force microscope, double-axis x-ray diffraction, and photoluminescence spectroscopy. It was demonstrated that, with the proper growth temperature and Si buffer thickness, the low-temperature Si buffer became tensily strained and reduced the lattice mismatch between the SiGe and the Si buffer layer. This performance is similar to that of the compliant substrate: a thin substrate that shares the mismatch strain in heteroepitaxy. Due to the smaller mismatch, misfit dislocation and threading dislocation densities were lower.
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22 January 2001
Research Article|
January 22 2001
Compliant effect of low-temperature Si buffer for SiGe growth Available to Purchase
Y. H. Luo;
Y. H. Luo
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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J. Wan;
J. Wan
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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R. L. Forrest;
R. L. Forrest
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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J. L. Liu;
J. L. Liu
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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G. Jin;
G. Jin
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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M. S. Goorsky;
M. S. Goorsky
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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K. L. Wang
K. L. Wang
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
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Y. H. Luo
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
J. Wan
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
R. L. Forrest
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
J. L. Liu
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
G. Jin
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
M. S. Goorsky
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
K. L. Wang
Device Research Laboratory, Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, California 900095-1594
Appl. Phys. Lett. 78, 454–456 (2001)
Article history
Received:
August 14 2000
Accepted:
November 06 2000
Citation
Y. H. Luo, J. Wan, R. L. Forrest, J. L. Liu, G. Jin, M. S. Goorsky, K. L. Wang; Compliant effect of low-temperature Si buffer for SiGe growth. Appl. Phys. Lett. 22 January 2001; 78 (4): 454–456. https://doi.org/10.1063/1.1337633
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