Accumulation capacitance for GaAs‐SiO₂ interfaces with Si interlayers Available to Purchase

We have studied the properties of metal‐oxide‐semiconductor (MOS) structures fabricated by remote plasma‐enhanced chemical vapor deposition of SiO₂ upon GaAs substrates. For n‐type GaAs, a silicon interlayer has been found to improve the interface properties. For our samples and this interlayer, integration of the quasi‐static capacitance curve indicates a band‐bending range of about 0.8 eV. For these samples, we observe a hysteresis of ∼0.6 V, and shifts of only 0.2 V in the midpoint of the rise from minimum to maximum capacitance upon changing frequency from 10 to 200 kHz at room temperature. Similar measurements for temperatures down to 80 K establish that even at such low temperatures an accumulation capacitance is observed. This sets an upper limit of about 70 meV for the separation between the interface Fermi level and the conduction‐band minimum. This limit is a factor of two smaller than the best previously reported limit for approach to the conduction band of GaAs in a MOS structure. Spectroscopic ellipsometry establishes that nearly 2 Å equivalent thickness of unoxidized silicon is at the SiO₂/GaAs interface.