We estimate the capacity requirement for optical input/output chips boosted by artificial intelligence in computing centers. It is expected that petabits per second (Pbps) capacity on a single chip may be achieved in ten years or so in laboratories. We then study the key challenges in the implementation of such photonic chips, focusing on technical bottlenecks such as laser integration, modulation speed, MUX/DEMUX scaling, photodetector efficiency, and packaging density. We also discuss potential solutions, including novel materials and integration techniques, to enhance performance and reduce power consumption. Our analysis suggests that significant innovations in these areas could lead to the development of compact and efficient Pbps photonic chips by 2035, paving the way for next-generation optical interconnect systems.
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