This Letter pioneers an investigation into the influence of temperature on threshold voltage (VTH) instability under negative bias in ferroelectric charge trap gate stack (FEG) high electron mobility transistors. Based on the experimental stress condition, i.e., gate bias of −20 V and temperature (T) range from 30 to 150 °C, our findings reveal a unidirectional VTH shift with 30 °C < T < 90 °C, and transitioning to a bidirectional VTH shift at 90 °C ≤ T ≤ 150 °C. The observed VTH < 0 V can be ascribed to the emission of electrons from the trapping layer, prompted by the pre-poling of the ferroelectric (FE) layer and the presence of interface traps. In contrast, under high-temperature stress, where VTH > 0 V, it indicates the depletion of the two-dimensional electron gas electrons due to de-poling and saturation of the polarization in the reverse direction. Moreover, this phenomenon is consistent with extracted activation energies (Ea) of 0.55 ± 0.01 and 0.79 ± 0.01 eV. Additionally, the recovery characteristics validate the trapping/detrapping process.
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