We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm2, 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 × 106 instructions/s.

1.
F. C.
Williams
and
T.
Kilburn
, “
Electronic digital computers
,”
Nature
162
,
487
(
1948
).
2.
K. K.
Likharev
and
V. K.
Semenov
, “
RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock-frequency digital systems
,”
IEEE Trans. Appl. Supercond.
1
,
3
28
(
1991
).
3.
A.
Rylyakov
, “
New design of single-bit all-digital RSFQ autocorrelator
,”
IEEE Trans. Appl. Supercond.
7
,
2709
2712
(
1997
).
4.
N.
Yoshikawa
and
Y.
Kato
, “
Reduction of power consumption of RSFQ circuits by inductance-load biasing
,”
Supercond. Sci. Technol.
12
,
918
920
(
1999
).
5.
M.
Tanaka
,
M.
Ito
,
A.
Kitayama
,
T.
Kouketsu
, and
A.
Fujimaki
, “
18-GHz, 4.0-aJ/bit operation of ultra-low-energy rapid single-flux-quantum shift registers
,”
Jpn. J. Appl. Phys.
51
,
053102
(
2012
).
6.
D. E.
Kirichenko
,
S.
Sarwana
, and
A. F.
Kirichenko
, “
Zero static power dissipation biasing of RSFQ circuits
,”
IEEE Trans. Appl. Supercond.
21
,
776
779
(
2011
).
7.
M. H.
Volkmann
,
A.
Sahu
,
C. J.
Fourie
, and
O. A.
Mukhanov
, “
Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation
,”
Supercond. Sci. Technol.
26
,
015002
(
2013
).
8.
Q. P.
Herr
,
A. Y.
Herr
,
O. T.
Oberg
, and
A. G.
Ioannidis
, “
Ultra-low-power superconductor logic
,”
J. Appl. Phys.
109
,
103903
(
2011
).
9.
N.
Takeuchi
,
D.
Ozawa
,
Y.
Yamanashi
, and
N.
Yoshikawa
, “
An adiabatic quantum flux parametron as an ultra-low-power logic device
,”
Supercond. Sci. Technol.
26
,
035010
(
2013
).
10.
D. S.
Holmes
,
A. L.
Ripple
, and
M. A.
Manheimer
, “
Energy-efficient superconducting computing—Power budgets and requirements
,”
IEEE Trans. Appl. Supercond.
23
,
1701610
(
2013
).
11.
M.
Dorojevets
,
P.
Bunyk
, and
D.
Zinoviev
, “
FLUX chip: Design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-μm LTS technology
,”
IEEE Trans. Appl. Supercond.
11
,
326
332
(
2001
).
12.
A.
Fujimaki
,
M.
Tanaka
,
T.
Yamada
,
Y.
Yamanashi
,
H.
Park
, and
N.
Yoshikawa
, “
Bit-serial single flux quantum microprocessor CORE
,”
IEICE Trans. Electron.
E91-C
,
342
349
(
2008
).
13.
C. L.
Ayala
,
T.
Tanaka
,
R.
Saito
,
M.
Nozoe
,
N.
Takeuchi
, and
N.
Yoshikawa
, “
MANA: A monolithic adiabatic integration architecture microprocessor using 1.4-zJ/op unshunted superconductor Josephson junction devices
,”
IEEE J. Solid-State Circuits
56
,
1152
1165
(
2021
).
14.
M.
Tanaka
,
Y.
Yamanashi
,
N.
Irie
,
H.-J.
Park
,
S.
Iwasaki
,
K.
Takagi
,
K.
Taketomi
,
A.
Fujimaki
,
N.
Yoshikawa
,
H.
Terai
, and
S.
Yorozu
, “
Design and implementation of a pipelined 8 bit-serial single-flux-quantum microprocessor with cache memories
,”
Supercond. Sci. Technol.
20
,
S305
S309
(
2007
).
15.
Y.
Hironaka
,
Y.
Yamanashi
, and
N.
Yoshikawa
, “
Demonstration of a single-flux-quantum microprocessor operating with Josephson-CMOS hybrid memory
,”
IEEE Trans. Appl. Supercond.
30
,
1301206
(
2020
).
16.
M.
Tanaka
,
K.
Takata
,
T.
Kawaguchi
,
Y.
Ando
,
N.
Yoshikawa
,
R.
Sato
,
A.
Fujimaki
,
K.
Takagi
, and
N.
Takagi
, “
Development of bit-serial RSFQ microprocessors integrated with shift-register-based random access memories
,” in
2015 15th International Superconductive Electronics Conference (ISEC)
(
IEEE
,
2015
), pp.
1
3
.
17.
M.
Tanaka
,
R.
Sato
,
Y.
Hatanaka
, and
A.
Fujimaki
, “
High-density shift-register-based rapid single-flux-quantum memory system for bit-serial microprocessors
,”
IEEE Trans. Appl. Supercond.
26
,
1301005
(
2016
).
18.
R.
Sato
,
Y.
Hatanaka
,
Y.
Ando
,
M.
Tanaka
,
A.
Fujimaki
,
K.
Takagi
, and
N.
Takagi
, “
High-speed operation of random-access-memory-embedded microprocessor with minimal instruction set architecture based on rapid single-flux-quantum logic
,”
IEEE Trans. Appl. Supercond.
27
,
1300505
(
2017
).
19.
S.
Nagasawa
,
K.
Hinode
,
T.
Satoh
,
M.
Hidaka
,
H.
Akaike
,
A.
Fujimaki
,
N.
Yoshikawa
,
K.
Takagi
, and
N.
Takagi
, “
Nb 9-layer fabrication process for superconducting large-scale SFQ circuits and its process evaluation
,”
IEICE Trans. Electron.
E97.C
,
132
140
(
2014
).
20.
Y.
Yamanashi
,
T.
Kainuma
,
N.
Yoshikawa
,
I.
Kataeva
,
H.
Akaike
,
A.
Fujimaki
,
M.
Tanaka
,
N.
Takagi
,
S.
Nagasawa
, and
M.
Hidaka
, “
100 GHz demonstrations based on the single-flux-quantum cell library for the 10 kA/cm2 Nb multi-layer process
,”
IEICE Trans. Electron.
E93.C
,
440
444
(
2010
).
21.
A.
Fujimaki
,
M.
Tanaka
,
R.
Kasagi
,
K.
Takagi
,
M.
Okada
,
Y.
Hayakawa
,
K.
Takata
,
H.
Akaike
,
N.
Yoshikawa
,
S.
Nagasawa
,
K.
Takagi
, and
N.
Takagi
, “
Large-scale integrated circuit design based on a Nb nine-layer structure for reconfigurable data-path processors
,”
IEICE Trans. Electron.
E97.C
,
157
165
(
2014
).
22.
E. S.
Fang
and
T. V.
Duzer
, “
A Josephson integrated circuit simulator (JSIM) for superconductive electronics application
,” in
Ext. Abst. 1989 International Superconductivity Electronics Conf. (ISEC '89)
(
IEEE
,
Tokyo
,
1989
), pp.
407
410
.
23.
Y.
Yamanashi
,
M.
Tanaka
,
A.
Akimoto
,
H.
Park
,
Y.
Kamiya
,
N.
Irie
,
N.
Yoshikawa
,
A.
Fujimaki
,
H.
Terai
, and
Y.
Hashimoto
, “
Design and implementation of a pipelined bit-serial SFQ microprocessor, CORE1β
,”
IEEE Trans. Appl. Supercond.
17
,
474
477
(
2007
).
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