We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm2, 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 × 106 instructions/s.
Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency
Masamitsu Tanaka, Ryo Sato, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi; Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency. Appl. Phys. Lett. 8 May 2023; 122 (19): 192601. https://doi.org/10.1063/5.0148273
Download citation file: