Chalcogenide superlattice (CSL) is one of the emerging material technologies for ultralow-power phase change memories. However, the resistance switching mechanism of the CSL-based device is still hotly debated. Early electrical measurements and recent materials characterizations have suggested that the Kooi-phase CSL is very likely to be the as-fabricated low-resistance state. Due to the difficulty in in situ characterization at atomic resolution, the structure of the electrically switched CSL in its high-resistance state is still unknown and mainly investigated by theoretical modelings. So far, there has been no simple model that can unify experimental results obtained from device-level electrical measurements and atomic-level materials characterizations. In this work, we carry out atomistic transport modelings of the CSL-based device and propose a simple mechanism accounting for its high resistance. The modeled high-resistance state is based on the interfacial SbTe bilayer flipped CSL that has previously been mistaken for the low-resistance state. This work advances the understanding of CSL for emerging memory applications.
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