Impact of area scaling on the ferroelectric properties of back-end of line compatible Hf_0.5Zr_0.5O₂ and Si:HfO₂-based MFM capacitors

Scaling of planar HfO₂-based ferroelectric capacitors is investigated experimentally by varying the capacitor area within five orders of magnitude, under the scope of a limited thermal budget for crystallization. Both Hf_0.5Zr_0.5O₂ (HZO) and Si-doped HfO₂ (HSO)-based metal/ferroelectric/metal capacitors with a 10 nm dielectric film thickness and TiN electrodes are demonstrated to be ferroelectric when integrated in a back-end of line (BEOL) of 130 nm CMOS technology, with a maximum thermal budget below 500 °C. When the area of the ferroelectric capacitors is scaled down from 7850 μm² to 0.28 μm², no degradation of the remanent polarization (2·P_R > 10 μC/cm² for HSO, > 30 μC/cm² for HZO) or of the switching kinetics (down to 100 ns at 3 V) is observed. Significant improvement of the field cycling endurance is demonstrated upon area scaling, consistent with the reduction of the total number of defects when devices are shrunk. The results pave the way for future BEOL demonstrations in 130 nm and more advanced nodes with record endurance similar to perovskite ferroelectrics.