We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets of devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 samples have a p-doped channel and an n-p-n gate stack. From experimental results, we demonstrate the superior performance of the transistor structure with a p-GaN channel/Al2O3 gate insulator in terms of dc performance. In addition, we demonstrate that Gen2 devices have highly stable threshold voltage, thus representing ideal devices for power electronic applications. Insight into the trapping processes in the two generations of devices was obtained by modeling the threshold voltage variations via differential rate equations.
Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator
Note: This paper is part of the Special Topic on Ultrawide Bandgap Semiconductors.
Maria Ruzzarin, Carlo De Santi, Feng Yu, Muhammad Fahlesa Fatahilah, Klaas Strempel, Hutomo Suryo Wasisto, Andreas Waag, Gaudenzio Meneghesso, Enrico Zanoni, Matteo Meneghini; Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator. Appl. Phys. Lett. 16 November 2020; 117 (20): 203501. https://doi.org/10.1063/5.0027922
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