Thermally varying hysteretic gate operation in few-layer and back gate field effect transistors (FETs) is studied and compared for memory applications. Clockwise hysteresis at room temperature and anti-clockwise hysteresis at higher temperature (373 K for and 400 K for ) are accompanied by step-like jumps in transfer curves for both forward and reverse voltage sweeps. Hence, a step-like conductance (STC) crossover hysteresis between the transfer curves for the two sweeps is observed at high temperature. Furthermore, memory parameters such as the RESET-to-WRITE window and READ window are defined and compared for clockwise hysteresis at low temperature and STC-type hysteresis at high temperature, showing better memory performance for FETs as compared to FETs. Smaller operating temperature and voltage along with larger READ and RESET-to-WRITE windows make FETs a better choice for thermally aided memory applications. Finally, temperature dependent Kelvin probe force microscopy measurements show decreasing (constant) surface potential with increasing temperature for (). This indicates less effective intrinsic trapping at high temperature in , leading to earlier occurrence of STC-type hysteresis in FETs as compared to FETs with increasing temperature.
Enhanced thermally aided memory performance using few-layer transistors
Natasha Goyal, David M. A. Mackenzie, Vishal Panchal, Himani Jawa, Olga Kazakova, Dirch Hjorth Petersen, Saurabh Lodha; Enhanced thermally aided memory performance using few-layer transistors. Appl. Phys. Lett. 3 February 2020; 116 (5): 052104. https://doi.org/10.1063/1.5126809
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