Enhanced n-type β-Ga₂O₃ $(2¯01)$ gate stack performance using Al₂O₃/SiO₂ bi-layer dielectric

High performance gate stacks are critically needed for the development of β-Ga₂O₃ power transistors. Significant improvement in the performance of β-Ga₂O₃ gate stacks is demonstrated in this work by using SiO₂ as an interlayer dielectric between Al₂O₃ and β-Ga₂O₃. The presence of SiO₂ results in an 800× reduction in gate leakage current along with a 1.7× increase in the electric breakdown field. Additionally, the capacitance-voltage characteristics show an increase in flat band voltage (from 0.74 V to 3.25 V) that can enable normally off power transistors. The lowest interface trap density (D_it) of 5.1 × 10¹⁰ cm⁻² eV⁻¹ for the SiO₂/β-Ga₂O₃ interface has been demonstrated through the use of a piranha clean before SiO₂ deposition on β-Ga₂O₃ for the first time. Reduction (8×) in D_it, hysteresis (from 0.17 V to 0.05 V), and border trap density indicate substantial improvement in the quality of the β-Ga₂O₃/gate dielectric interface for the Al₂O₃/SiO₂ bilayer stack as compared to only Al₂O₃.