High performance gate stacks are critically needed for the development of β-Ga2O3 power transistors. Significant improvement in the performance of β-Ga2O3 gate stacks is demonstrated in this work by using SiO2 as an interlayer dielectric between Al2O3 and β-Ga2O3. The presence of SiO2 results in an 800× reduction in gate leakage current along with a 1.7× increase in the electric breakdown field. Additionally, the capacitance-voltage characteristics show an increase in flat band voltage (from 0.74 V to 3.25 V) that can enable normally off power transistors. The lowest interface trap density (Dit) of 5.1 × 1010 cm−2 eV−1 for the SiO2/β-Ga2O3 interface has been demonstrated through the use of a piranha clean before SiO2 deposition on β-Ga2O3 for the first time. Reduction (8×) in Dit, hysteresis (from 0.17 V to 0.05 V), and border trap density indicate substantial improvement in the quality of the β-Ga2O3/gate dielectric interface for the Al2O3/SiO2 bilayer stack as compared to only Al2O3.
Enhanced n-type β-Ga2O3 gate stack performance using Al2O3/SiO2 bi-layer dielectric
Dipankar Biswas, Chandan Joishi, Jayeeta Biswas, Kartikey Thakar, Siddharth Rajan, Saurabh Lodha; Enhanced n-type β-Ga2O3 gate stack performance using Al2O3/SiO2 bi-layer dielectric. Appl. Phys. Lett. 27 May 2019; 114 (21): 212106. https://doi.org/10.1063/1.5089627
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