TiN/Al₂O₃/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al₂O₃ gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al₂O₃/ZnO interface and the ZnO layer are defective just after the Al₂O₃ layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al₂O₃ deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al₂O₃/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al₂O₃ deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al₂O₃ deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.