We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.
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28 July 2014
Research Article|
July 31 2014
Ion traps fabricated in a CMOS foundry
K. K. Mehta;
K. K. Mehta
a)
1Department of Electrical Engineering and Computer Science,
Massachusetts Institute of Technology
, Cambridge, Massachusetts 02139, USA
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A. M. Eltony;
A. M. Eltony
a)
2Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics,
Massachusetts Institute of Technology
, Cambridge, Massachusetts 02139, USA
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C. D. Bruzewicz;
C. D. Bruzewicz
a)
3Lincoln Laboratory,
Massachusetts Institute of Technology
, Lexington, Massachusetts 02420, USA
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I. L. Chuang;
I. L. Chuang
2Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics,
Massachusetts Institute of Technology
, Cambridge, Massachusetts 02139, USA
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R. J. Ram;
R. J. Ram
1Department of Electrical Engineering and Computer Science,
Massachusetts Institute of Technology
, Cambridge, Massachusetts 02139, USA
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J. M. Sage;
J. M. Sage
b)
3Lincoln Laboratory,
Massachusetts Institute of Technology
, Lexington, Massachusetts 02420, USA
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J. Chiaverini
J. Chiaverini
c)
3Lincoln Laboratory,
Massachusetts Institute of Technology
, Lexington, Massachusetts 02420, USA
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K. K. Mehta
1,a)
A. M. Eltony
2,a)
C. D. Bruzewicz
3,a)
I. L. Chuang
2
R. J. Ram
1
J. M. Sage
3,b)
J. Chiaverini
3,c)
1Department of Electrical Engineering and Computer Science,
Massachusetts Institute of Technology
, Cambridge, Massachusetts 02139, USA
2Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics,
Massachusetts Institute of Technology
, Cambridge, Massachusetts 02139, USA
3Lincoln Laboratory,
Massachusetts Institute of Technology
, Lexington, Massachusetts 02420, USA
a)
K. K. Mehta, A. M. Eltony, and C. D. Bruzewicz contributed equally to this work.
Appl. Phys. Lett. 105, 044103 (2014)
Article history
Received:
June 17 2014
Accepted:
July 07 2014
Citation
K. K. Mehta, A. M. Eltony, C. D. Bruzewicz, I. L. Chuang, R. J. Ram, J. M. Sage, J. Chiaverini; Ion traps fabricated in a CMOS foundry. Appl. Phys. Lett. 28 July 2014; 105 (4): 044103. https://doi.org/10.1063/1.4892061
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