A three-dimensional (3D) double-layer HfO2-based vertical-resistive random access memory (VRRAM) with low-resistivity C54-TiSi2 as horizontal electrodes is demonstrated using complementary metal-oxide semiconductor processing. The electrical measurements show bipolar resistive switching by using C54-TiSi2 as electrodes for resistive switching (RS) applications. The statistical analysis exhibits cycle-to-cycle and cell-to-cell stable non-volatile properties with robust endurance (100 cycles) and long term data retention (104 s), suggesting that the ultrathin sidewall of C54-TiSi2 nanoscale electrodes serve to confine and stabilize the random nature of the conducting nanofilaments. The superior RS characteristics demonstrated here highlight the applicability of C54-TiSi2 sidewall-confinement nanoscale electrodes to VRRAM.
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3 November 2014
Research Article|
November 04 2014
Low-resistivity C54-TiSi2 as a sidewall-confinement nanoscale electrode for three-dimensional vertical resistive memory
José Ramón Durán Retamal;
José Ramón Durán Retamal
1Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division,
King Abdullah University of Science and Technology (KAUST)
, Thuwal 23955-6900, Kingdom of Saudi Arabia
2Institute of Photonics and Optoelectronics and Department of Electrical Engineering,
National Taiwan University
, Taipei 10617, Taiwan
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Chen-Fang Kang;
Chen-Fang Kang
1Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division,
King Abdullah University of Science and Technology (KAUST)
, Thuwal 23955-6900, Kingdom of Saudi Arabia
2Institute of Photonics and Optoelectronics and Department of Electrical Engineering,
National Taiwan University
, Taipei 10617, Taiwan
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Po-Kang Yang;
Po-Kang Yang
2Institute of Photonics and Optoelectronics and Department of Electrical Engineering,
National Taiwan University
, Taipei 10617, Taiwan
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Chuan-Pei Lee;
Chuan-Pei Lee
2Institute of Photonics and Optoelectronics and Department of Electrical Engineering,
National Taiwan University
, Taipei 10617, Taiwan
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Der-Hsien Lien;
Der-Hsien Lien
2Institute of Photonics and Optoelectronics and Department of Electrical Engineering,
National Taiwan University
, Taipei 10617, Taiwan
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Chih-Hsiang Ho;
Chih-Hsiang Ho
3Department of Electrical and Computer Engineering,
Purdue University
, West Lafayette, Indiana 47907, USA
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José Ramón Durán Retamal
1,2
Chen-Fang Kang
1,2
Po-Kang Yang
2
Chuan-Pei Lee
2
Der-Hsien Lien
2
Chih-Hsiang Ho
3
Jr-Hau He
1,a)
1Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division,
King Abdullah University of Science and Technology (KAUST)
, Thuwal 23955-6900, Kingdom of Saudi Arabia
2Institute of Photonics and Optoelectronics and Department of Electrical Engineering,
National Taiwan University
, Taipei 10617, Taiwan
3Department of Electrical and Computer Engineering,
Purdue University
, West Lafayette, Indiana 47907, USA
a)
Author to whom correspondence should be addressed. Electronic mail: [email protected]
Appl. Phys. Lett. 105, 182101 (2014)
Article history
Received:
August 23 2014
Accepted:
October 14 2014
Citation
José Ramón Durán Retamal, Chen-Fang Kang, Po-Kang Yang, Chuan-Pei Lee, Der-Hsien Lien, Chih-Hsiang Ho, Jr-Hau He; Low-resistivity C54-TiSi2 as a sidewall-confinement nanoscale electrode for three-dimensional vertical resistive memory. Appl. Phys. Lett. 3 November 2014; 105 (18): 182101. https://doi.org/10.1063/1.4901072
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