A device model of silicon carbide (SiC) p- and n-channel junction field-effect transistors (JFETs) applicable in a high-temperature range was constructed, and the validity of the model was evaluated in Simulation Program with Integrated Circuit Emphasis (SPICE) simulations. The constructed device model well reproduced the electrical characteristics of the JFETs fabricated in our previous study over a wide temperature range from room temperature to 573 K. Furthermore, the static and dynamic characteristics of a SiC complementary JFET inverter were simulated with the constructed device model, and the temperature dependence of the logic threshold voltage showed good agreement, where the differences between the measurements and calculations were as small as 0.05 V.

Topics
Logic gates, Electrical properties and parameters, Field effect transistors, Integrated circuits, Semiconductor device modeling, Ion implantation

Silicon carbide (SiC) has been studied as one of the most promising materials for low-loss power device applications owing to its unique physical properties, such as a high critical electric field and wide bandgap.1,2 SiC Schottky barrier diodes and SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) have been commercially available since the 2010s.3 SiC is also promising for the application of integrated circuits (ICs) operating under high-temperature environments, such as automotive, space exploration, and deep-well drilling.4–6 Most commercially available ICs consist of silicon (Si) complementary metal–oxide–semiconductor (CMOS) devices, which cannot operate above 473 K due to the physical limit of Si. Then, Si CMOS on silicon-on-insulator (SOI) has been proposed, and operation at up to 573 K has been confirmed.7 On the other hand, SiC devices can operate in the temperature range in which Si devices cannot operate (⁠>573 K) since the intrinsic carrier density of SiC is much lower than that of Si. Furthermore, doping concentrations in the p- and n-type regions of SiC can be controlled over a wide range (1014–1019 cm−3) relatively easily by ion implantation,2 which is exceptional as a wide bandgap semiconductor material.

Several transistors are considered to be suitable for configuring ICs operational at high temperatures. High-temperature operations of SiC MOSFETs,8,9 bipolar junction transistors,10–13 and junction field-effect transistors (JFETs)14,15 have been reported. Among them, JFETs are expected to be more reliable than the other devices since the JFETs have stable threshold voltages over a wide temperature range and no gate oxide. Neudeck et al. reported that highly functional logic gates and memories were configured by SiC (depletion-mode) n-JFETs and resistors (JFET-R), and their operation at 773 K was demonstrated.15 One of the disadvantages of the JFET-R circuit, however, is its high static power consumption since the current continues to flow through the resistor and n-JFET even without an input signal.

A complementary JFET (CJFET) circuit can be assembled with p- and n-JFETs in the same manner as CMOS circuits. We have demonstrated normal transistor operations at up to 673 K of SiC p- and n-channel JFETs fabricated by ion implantation into a high-purity semi-insulating (HPSI) SiC substrate.16,17 Moreover, operations of SiC CJFET logic gates were demonstrated from room temperature to 623 K.18 

For the fabrication of SiC CJFET logic gates and memories, device models of SiC p- and n-JFETs that predict their electrical characteristics from room temperature to high temperature are required to design a circuit and perform simulations. In prior works, a first-order Simulation Program with Integrated Circuit Emphasis (SPICE) modeling for SiC n-JFETs operating at high temperatures was reported.19–21 In their model, parameter fitting was performed based on n-channel MOSFET, which is not practical for calculating n-JFETs with different structural parameters. The SPICE model using gradual channel approximation and abrupt depletion approximation for JFETs was originally proposed for Si JFETs.22–24 While there exist some reports on SiC n-JFET physics-based device models,25,26 they are supposed to be applied to n-JFETs for power device applications, where operation at high temperature (⁠>473 K) is not considered. Moreover, a SiC p-JFET device model has not been reported.

In this study, device models of SiC p- and n-JFETs are developed for the circuit design of SiC CJFET. The electrical characteristics of SiC p- and n-JFETs were calculated based on Makris’s model in Ref. 27, considering incomplete ionization of dopants. Note that equations are derived in a procedure different from the prior model.27 The current–voltage characteristics of SiC p- and n-JFETs were calculated with the developed device model and compared with the experimental data. The temperature dependence of the subthreshold slopes showed good agreement with the measured ones at up to 573 K. In addition, the characteristics of a SiC CJFET inverter were simulated, and the results agreed well with the experimental ones within a wide temperature range.

Figure 1 shows a schematic diagram of p- and n-JFETs fabricated in our previous study. The JFETs have side-gate structures where two gates are horizontally placed beside the channel. Figure 2 shows the schematic top and cross-sectional views of a side-gate n-JFET. ND,ch, NA,G, Ln, Wn, and an are the donor concentration in the channel region, the acceptor concentration in the gate region, the channel length, the channel width, and the channel thickness of an n-JFET, respectively. Then, the device structure is the same as that considered in Ref. 27, and we constructed the device model based on the literature. The energy band diagrams at x = x′ and y = 0 are depicted in Figs. 3(a) and 3(b), respectively. The Poisson equation in the y-direction at x = x′ under gradual channel approximation is given by the following equation:28,
(1)
Here, ψn(y), q, ɛ, nch(y), ni, EFn(x′), Ei(y), kB, T, Vn(x′), and UT are the electrostatic potential in the channel region, the elementary charge, the permittivity in the semiconductor, the electron density in the channel region, the intrinsic carrier concentration, the quasi-Fermi level, the intrinsic Fermi level, the Boltzmann’s constant, temperature, the potential difference between x = 0 and x = x′, and the thermal voltage, respectively. Using the finite difference method, the second order differential of ψn(y) can be approximated as28,
(2)
where ψs,n = ψn(±a/2) and ψ0,n = ψn(0). Thus, setting y = 0 in Eq. (1), the relationship between ψs,n and ψ0,n is given by
(3)
The mobile charge (areal) density, which corresponds to the electrons in the channel region contributing to the drain current, can be expressed as the following equation:27,28 
(4)
where bn = 8qND,chɛ and Qf,n = qND,chan (the donor charge density in the channel region). Although the above equation is the same as that mobile charge density obtained assuming that the channel region consists of a fully depleted (band bending) region and a (flatband) region with a charge-neutral condition, Eq. (4) has been derived in a different procedure. Equation (4) is obtained by substituting Eq. (6) into Eq. (9) in Ref. 27. These equations are obtained (in the literature) assuming that the accumulation term can be omitted and the pinch-off voltage is much larger than the thermal voltage. Here, the first term in Eq. (4) (bn(ψ0,n−ψs,n)) coincides with the space charge of the two depletion layers in the channel region under depletion approximation, whereas depletion approximation is not assumed in the derivation. Using bn and Qf,n, Eq. (3) is rewritten as
(5)
Then, the relationship between Qm,n and Vn(x′) is given by
(6)
Here, Vbi,n is defined as Vbi,n=UT⁡ln(ND,chNA,G/ni2) and the following equations:
(7)
(8)
are considered.
FIG. 1.
Schematic structures of SiC side-gate p- and n-JFETs.17
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Schematic structures of SiC side-gate p- and n-JFETs.17 

FIG. 1.
Schematic structures of SiC side-gate p- and n-JFETs.17
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Schematic structures of SiC side-gate p- and n-JFETs.17 

Close modal
FIG. 2.
Schematic (a) top and (b) side views of a side-gate n-JFET.
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Schematic (a) top and (b) side views of a side-gate n-JFET.

FIG. 2.
Schematic (a) top and (b) side views of a side-gate n-JFET.
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Schematic (a) top and (b) side views of a side-gate n-JFET.

Close modal
FIG. 3.
Energy band diagram of a side-gate n-JFET along (a) the y-axis at x = x′ and (b) the x-axis at y = 0.
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Energy band diagram of a side-gate n-JFET along (a) the y-axis at x = x′ and (b) the x-axis at y = 0.

FIG. 3.
Energy band diagram of a side-gate n-JFET along (a) the y-axis at x = x′ and (b) the x-axis at y = 0.
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Energy band diagram of a side-gate n-JFET along (a) the y-axis at x = x′ and (b) the x-axis at y = 0.

Close modal
In the previous model,27 the dopant in the channel region was assumed to be fully ionized. In SiC, however, the ionization energy of dopants (nitrogen or phosphorus for n-type doping and aluminum for p-type doping) is not small, and incomplete ionization should be considered, especially for p-JFETs. Then, the drain current equation (in an n-JFET) used in Ref. 27 is corrected as follows:
(9)
where μe and ηn are the electron mobility and the ionization ratio of the donors in the channel, respectively. Although the ionization ratio can depend on the position inside the channel according to the difference between static and quasi-Fermi potential, we assume that the ionization ratio is constant over the entire channel region for simplicity in this study. It should be noted that incomplete ionization affects potential distribution and changes the threshold voltage of JFETs, which is not implemented for the sake of simplicity in this study. dVn(x)/dx is obtained by replacing x′ by x in Eq. (6) and differentiating both sides of Eq. (6) by x,
(10)
Integrating both sides of Eq. (9) from x = 0 (source) to x = Ln (drain), the following equation is obtained:
(11)
Then, considering that the drain current is independent of x, the left-hand side of Eq. (11) is expressed as ∫0LnID,ndx=ID,nLn. Therefore, the drain current is obtained as
(12)
where Qm,nS and Qm,nD are the mobile charge density at x = 0 (source) and x = Ln (drain), respectively, and fn(Qm,n) is defined as
(13)
In the same way as an n-JFET, the drain current in a p-JFET ID,p can be derived as the following equations:
(14)
(15)
where μh and ηp are the hole mobility and the ionization ratio of the acceptors in the channel, respectively. bp and Qf,p are defined as bp = 8qNA,chɛ and Qf,p = qNA,chap. Qm,p is expressed as
(16)
In the present model, parasitic resistances and capacitances are not modeled. For calculating dynamic characteristics in circuits with JFET loads, such parasitic resistances and capacitances are required, the modeling of which is our future study.
ηn = nch/ND,ch and ηp = pch/NA,ch are calculated by solving the neutrality equations,29,
(17)
(18)
Here, pch, gD (gA), NC (NV), and ΔED,i (ΔEA,i) are the hole density in the channel region of a p-JFET, the degeneracy factor of the donor (acceptor), the effective density of states in the conduction band (valence band), and the ionization energy of the donor (acceptor) at i-site (i = h, k), respectively. gD and gA were substituted by 2 and 4, respectively. ΔED,i and ΔEA,i become smaller with increasing the doping concentration and are expressed as the following equations:30,
(19)
(20)
where ΔED,i0 (ΔEA,i0) is the ionization energy of the donor (acceptor) in the lightly doped SiC, and ΔED,h0, ΔED,k0, ΔEA,h0, and ΔEA,k0 are set to 60, 120, 198, and 201 meV, respectively.3, α is a parameter and is set to 4 × 10−8 eV cm.3, μe and μh expressions reported in Refs. 31 and 32 are adopted in our device model, which are expressed as the following equations:
(21)
(22)
Here, μmin=40×T300 K−0.5 cm2/Vs⁠, μmax=950×T300 K−2.4 cm2/Vs⁠, and Nref=2×1017×T300 K cm−3⁠. Short-channel effects are not considered in this model. When comparing the experimental and calculated characteristics, we chose JFETs with long channel devices where short-channel effects do not occur.33 All circuit simulations were conducted in SmartSpice by Silvaco.34 Note that source or drain parasitic resistances were not considered in the simulation.

Figures 4 and 5 depict ID1/2–VG curves on a linear scale and ID–VG characteristics on a semi-log scale of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K, respectively. The solid lines and symbols denote the calculated results with our device model and the measurement results of the JFETs fabricated in our previous study.17 The major parameters in the calculations are shown in Table I. The doping concentrations are the same as those of the designed values, and the channel length, width, and thickness are the fitting parameters. The fitting parameters were fitted as temperature independent. The extracted values are slightly different from the designed ones due to the lateral straggling of the implanted atoms.35,36 The device model constructed in this study well reproduced the electrical characteristics of the fabricated devices within all the measurement temperature ranges.

FIG. 4.
(a)–(d) ID1/2–VG curves of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K. Open square symbols and solid lines represent the experimental17 and simulated results, respectively.
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(a)–(d) ID1/2–VG curves of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K. Open square symbols and solid lines represent the experimental17 and simulated results, respectively.

FIG. 4.
(a)–(d) ID1/2–VG curves of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K. Open square symbols and solid lines represent the experimental17 and simulated results, respectively.
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(a)–(d) ID1/2–VG curves of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K. Open square symbols and solid lines represent the experimental17 and simulated results, respectively.

Close modal
FIG. 5.
(a)–(d) ID–VG characteristics of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K on a semi-log scale. Open square symbols and solid lines denote the experimental17 and simulated results, respectively.37
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(a)–(d) ID–VG characteristics of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K on a semi-log scale. Open square symbols and solid lines denote the experimental17 and simulated results, respectively.37 

FIG. 5.
(a)–(d) ID–VG characteristics of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K on a semi-log scale. Open square symbols and solid lines denote the experimental17 and simulated results, respectively.37
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(a)–(d) ID–VG characteristics of SiC p- and n-JFETs at |VD| = 2 V from 300 to 573 K on a semi-log scale. Open square symbols and solid lines denote the experimental17 and simulated results, respectively.37 

Close modal
TABLE I.

Major parameters used in simulations of the characteristics of SiC p- and n-JFETs extracted by fitting to the experimental results.

p-JFETn-JFET
ParameterValueParameterValue
NA,ch 5 × 1016 cm−3 ND,ch 5 × 1016 cm−3 
ND,G 5 × 1019 cm−3 NA,G 5 × 1019 cm−3 
Wp/Lp 0.3 μm/3.3 μm Wn/Ln 0.6 μm/3.3 μm 
ap 460 nm an 374 nm 
p-JFETn-JFET
ParameterValueParameterValue
NA,ch 5 × 1016 cm−3 ND,ch 5 × 1016 cm−3 
ND,G 5 × 1019 cm−3 NA,G 5 × 1019 cm−3 
Wp/Lp 0.3 μm/3.3 μm Wn/Ln 0.6 μm/3.3 μm 
ap 460 nm an 374 nm 
View Large

Figure 6 shows the temperature dependence of Vth from 300 to 573 K. Closed circle and open square symbols represent the calculated data by the model constructed in this study and the measured data,17 respectively. Those results agreed well from 300 to 573 K, and the differences between the measured and calculated results by our model were less than 0.05 V.

FIG. 6.
Temperature dependence of threshold voltage Vth in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively.
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Temperature dependence of threshold voltage Vth in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively.

FIG. 6.
Temperature dependence of threshold voltage Vth in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively.
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Temperature dependence of threshold voltage Vth in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively.

Close modal
An analytical model (not our device model) describes the drain current of SiC p- and n-JFETs in the saturation region (IDp, IDn) by the following equations:38 
(23)
(24)
(25)
(26)
where βn (βp), Vth,n (Vth,p), pG (nG) are the transconductance parameter, the threshold voltage, and the hole (electron) concentration in the gate of an n-JFET (a p-JFET), respectively.

The temperature dependence of the transconductance parameters was obtained from the slope of the ID1/2–VG characteristics. Figure 7 depicts the temperature dependence of βn and βp. Closed circle symbols, open square symbols, and dashed lines denote the simulated values by the developed device model, the experimental values,17 and the theoretical estimations by Eqs. (24) and (26), respectively. Since the transconductance parameters cannot be expressed in analytical equations from the model provided in this study, βn and βp are extracted in the same way as obtained from the experimental curves. βn decreased with elevating the temperature due to the decrease in μe. On the other hand, βp increased from room temperature to 473 K owing to the increase in pch caused by the enhanced ionization of Al acceptors and decreased above 473 K due to the decrease in μh. βp for the simulated and fabricated p-JFETs gradually deviates with elevating the temperature from 423 K. The current flowing through not only the channel region but also the undoped region in the HPSI SiC substrate, in which the resistivity becomes lower with elevating the temperature,39 may cause the differences in βp at higher temperatures. Owing to the βp difference, the output characteristics of the fabricated p-JFETs show a slight deviation from those calculated by the model (not shown). Model refining is required, especially for p-JFET, to achieve further accurate simulation.

FIG. 7.
(a) and (b) Temperature dependence of transconductance parameter β in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively. Dashed lines denote the theoretical β predicted by the temperature dependence of the carrier mobility and the carrier concentration.38
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(a) and (b) Temperature dependence of transconductance parameter β in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively. Dashed lines denote the theoretical β predicted by the temperature dependence of the carrier mobility and the carrier concentration.38 

FIG. 7.
(a) and (b) Temperature dependence of transconductance parameter β in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively. Dashed lines denote the theoretical β predicted by the temperature dependence of the carrier mobility and the carrier concentration.38
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(a) and (b) Temperature dependence of transconductance parameter β in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols correspond to the experimental17 and simulated data, respectively. Dashed lines denote the theoretical β predicted by the temperature dependence of the carrier mobility and the carrier concentration.38 

Close modal

Figure 8 depicts the temperature dependence of the subthreshold swing (SS) extracted from ID–VG characteristics. The closed circle and open square symbols denote the calculated and measured data,17 respectively. The dashed lines indicate the theoretical limit of SS in a JFET.40 Although the measured SS was slightly larger than the calculated and theoretical limits, the differences between the calculated and measured results were smaller than 15%.

FIG. 8.
(a) and (b) Temperature dependence of subthreshold swing SS in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols represent the experimental17 and simulated data, respectively. Dashed lines correspond to the theoretical limit of SS.40
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(a) and (b) Temperature dependence of subthreshold swing SS in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols represent the experimental17 and simulated data, respectively. Dashed lines correspond to the theoretical limit of SS.40 

FIG. 8.
(a) and (b) Temperature dependence of subthreshold swing SS in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols represent the experimental17 and simulated data, respectively. Dashed lines correspond to the theoretical limit of SS.40
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(a) and (b) Temperature dependence of subthreshold swing SS in SiC p- and n-JFETs from 300 to 573 K. Open square and closed circle symbols represent the experimental17 and simulated data, respectively. Dashed lines correspond to the theoretical limit of SS.40 

Close modal

Figure 9 depicts a schematic structure of the SiC CJFET inverter assembled with side-gate JFETs fabricated in our previous study and a circuit diagram of a CJFET inverter. Vin, Vout, and Vdd are the input voltage, the output voltage, and the supply voltage, respectively. The parameters used to calculate the characteristics of the CJFET inverter fabricated on an HPSI SiC substrate are shown in Table II, and Vdd was set to 1.4 V.

FIG. 9.
(a) A schematic structure of the SiC CJFET inverter fabricated in our previous study and (b) a circuit diagram of a CJFET inverter.
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(a) A schematic structure of the SiC CJFET inverter fabricated in our previous study and (b) a circuit diagram of a CJFET inverter.

FIG. 9.
(a) A schematic structure of the SiC CJFET inverter fabricated in our previous study and (b) a circuit diagram of a CJFET inverter.
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(a) A schematic structure of the SiC CJFET inverter fabricated in our previous study and (b) a circuit diagram of a CJFET inverter.

Close modal
TABLE II.

Major parameters used in simulations of the characteristics of a SiC CJFET inverter.

p-JFETn-JFET
ParameterValueParameterValue
NA,ch 5 × 1016 cm−3 ND,ch 5 × 1016 cm−3 
ND,G 5 × 1019 cm−3 NA,G 5 × 1019 cm−3 
Wp/Lp 0.43 μm/4.0 μm Wn/Ln 0.56 μm/4.0 μm 
ap 434 nm an 430 nm 
p-JFETn-JFET
ParameterValueParameterValue
NA,ch 5 × 1016 cm−3 ND,ch 5 × 1016 cm−3 
ND,G 5 × 1019 cm−3 NA,G 5 × 1019 cm−3 
Wp/Lp 0.43 μm/4.0 μm Wn/Ln 0.56 μm/4.0 μm 
ap 434 nm an 430 nm 
View Large

The voltage transfer characteristics (VTCs) of a SiC CJFET inverter in a temperature range from 300 to 573 K are shown in Fig. 10. Solid lines and symbols with dashed lines represent the simulated and experimental results,18 respectively. The SPICE simulations with the device model constructed in this study well reproduce the characteristics of the fabricated SiC CJFET inverter over a wide temperature range. At temperatures of 473 and 573 K, transition regions of the experimental VTC are slightly wider than the simulated VTC. The wider transition region may be due to the non-ideal leakage current mentioned in Sec. III A.

FIG. 10.
(a)–(d) Voltage transfer characteristics of the SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square symbols with dashed lines and solid lines represent the experimental18 and simulated results, respectively.37
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(a)–(d) Voltage transfer characteristics of the SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square symbols with dashed lines and solid lines represent the experimental18 and simulated results, respectively.37 

FIG. 10.
(a)–(d) Voltage transfer characteristics of the SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square symbols with dashed lines and solid lines represent the experimental18 and simulated results, respectively.37
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(a)–(d) Voltage transfer characteristics of the SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square symbols with dashed lines and solid lines represent the experimental18 and simulated results, respectively.37 

Close modal

The logic threshold voltages (Vlth) and noise margins are extracted from the VTCs shown in Fig. 10. In this study, Vlth was defined as Vin at the maximum of |dVout/dVin|. The temperature dependence of Vlth extracted from the VTCs is shown in Fig. 11. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively. The simulated Vlth agreed well with the experimental Vlth, and the differences between the simulated and experimental values are at most 0.05 V.

FIG. 11.
Temperature dependence of the logic threshold voltages in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.
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Temperature dependence of the logic threshold voltages in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.

FIG. 11.
Temperature dependence of the logic threshold voltages in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.
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Temperature dependence of the logic threshold voltages in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.

Close modal
The low and high noise margins (NML and NMH) were defined by the following equations:
(27)
(28)
where VIL and VOH are defined as Vin and Vout at dVout/dVin = −1 within a transition region in the VTCs from the high level of Vout to Vlth, and VIH and VOL are defined as Vin and Vout at dVout/dVin = −1 within a transition region in the VTCs from Vlth to the low level of Vout. The temperature dependences of the NML and NMH obtained from the VTCs are shown in Fig. 12. Closed circle and open square symbols are the simulated and experimental results,18 respectively. The simulated NML decreased and the simulated NMH increased with elevating the temperature, while both NML and NMH of the fabricated SiC CJFET inverter decreased. The slight deviation is caused by the wider transition regions in the experimental VTCs, which is due to the non-ideal leakage current in the fabricated CJFET inverter. In the simulated results, the transition region is narrow, and an NMH increase is observed due to the Vlth shift at higher temperatures.
FIG. 12.
(a) and (b) Temperature dependence of the noise margins in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.
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(a) and (b) Temperature dependence of the noise margins in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.

FIG. 12.
(a) and (b) Temperature dependence of the noise margins in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.
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(a) and (b) Temperature dependence of the noise margins in a SiC CJFET inverter at Vdd = 1.4 V from 300 to 573 K. Open square and closed circle symbols correspond to the experimental18 and simulated data, respectively.

Close modal

Figure 13 presents the dynamic characteristics of a SiC CJFET inverter in a temperature range of 300–573 K. Dashed and solid lines denote the simulated and experimental results, respectively. A voltage follower circuit assembled with an op-amp (LT1793, Linear Technology) was connected to the output of the probe station due to the high output impedance of the fabricated SiC CJFET inverter.18 Then, the load capacitance of 40 pF was connected to the output terminal of a SiC CJFET inverter in the SPICE simulations. As shown in Fig. 13, the simulations with our model well reproduced the output signals of the CJFET inverter fabricated in our previous study at up to 573 K. The rise and fall times (tr, tf) of the output signals were obtained as a time interval from 0% or 100% to 50%. The temperature dependences of tr and tf are shown in Fig. 14. tr and tf are inversely proportional to ID,p and ID,n, respectively. With elevating temperature, tr decreases due to the increase in ID,p. On the other hand, tf increases at higher temperatures, which is attributed to the decrease in ID,n. As shown in Fig. 14, the simulated and experimental data were close at 300–573 K. These results indicate that the characteristics of the fabricated CJFET circuits can be predicted with our device model within a wide temperature range. It should be noted that the tr and tf are small, and the maximum operational frequency is as low as a few kHz, which is attributed to the small transconductance of the fabricated JFET.18 

FIG. 13.
(a)–(d) Dynamic characteristics of a SiC CJFET inverter at up to 573 K. Solid lines and dashed lines represent the experimental18 and simulated results, respectively.
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(a)–(d) Dynamic characteristics of a SiC CJFET inverter at up to 573 K. Solid lines and dashed lines represent the experimental18 and simulated results, respectively.

FIG. 13.
(a)–(d) Dynamic characteristics of a SiC CJFET inverter at up to 573 K. Solid lines and dashed lines represent the experimental18 and simulated results, respectively.
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(a)–(d) Dynamic characteristics of a SiC CJFET inverter at up to 573 K. Solid lines and dashed lines represent the experimental18 and simulated results, respectively.

Close modal
FIG. 14.
Temperature dependences of rise and fall times in a SiC CJFET inverter at Vdd = 1.4 V. Open and closed symbols represent the experimental18 and simulated results, respectively.
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Temperature dependences of rise and fall times in a SiC CJFET inverter at Vdd = 1.4 V. Open and closed symbols represent the experimental18 and simulated results, respectively.

FIG. 14.
Temperature dependences of rise and fall times in a SiC CJFET inverter at Vdd = 1.4 V. Open and closed symbols represent the experimental18 and simulated results, respectively.
View largeDownload slide

Temperature dependences of rise and fall times in a SiC CJFET inverter at Vdd = 1.4 V. Open and closed symbols represent the experimental18 and simulated results, respectively.

Close modal

The simulated results at elevated temperatures showed a slight difference from the experimental results. It is expected that the deviation can be minimized when the non-ideal leakage current is prevented. Since the non-ideal leakage current is likely due to the lower resistivity of the HPSI SiC substrate at high temperatures, the fabrication of SiC CJFET in a p- and n-well structure on an epitaxial layer like Si CMOS circuits (electrical isolation by p-n junctions) may be effective to reduce the leakage current, and the constructed device models are expected to show better agreement with the experimental results.

In this study, we have proposed a device model for SPICE simulations. As discussed in this paper, the proposed model successfully reproduces the experimental results for both single JFET and CJFET inverter circuit operations, demonstrating its applicability to logic circuit design. However, for analog circuit applications, a more precise model is required, which will be addressed in our future work.

The authors constructed a device model of SiC side-gate p- and n-JFETs and calculated the electrical characteristics of the SiC JFETs with the device model. The calculated and experimental results of ID–VG characteristics agreed well over a wide temperature range from 300 to 573 K. The temperature dependences of the calculated SS well reproduced the experimental SS extracted from the ID–VG characteristics. The results implied that the developed device model of both SiC p- and n-JFETs is valid at up to 573 K. The static characteristics of the SiC CJFET inverter were also calculated with the device model constructed in this study. The simulated Vlth showed good agreement with the experimental results within the wide temperature range. The authors believe that the device model presented in this study is promising for the SiC CJFET circuit design and will lead to further development of the SiC CJFET circuits.

We gratefully acknowledge the financial support in the form of Kakenhi Grants-in-Aid (No. 24K17307) from the Japan Society for the Promotion of Science (JSPS) and a research grant from the Murata Science Foundation.

The authors have no conflicts to disclose.

Noriyuki Maeda: Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (lead); Visualization (lead); Writing – original draft (lead). Mitsuaki Kaneko: Conceptualization (lead); Funding acquisition (supporting); Project administration (lead); Resources (supporting); Supervision (lead); Validation (lead); Writing – original draft (supporting); Writing – review & editing (lead). Hajime Tanaka: Validation (equal); Writing – review & editing (lead). Tsunenobu Kimoto: Funding acquisition (lead); Project administration (supporting); Resources (lead); Supervision (equal); Writing – review & editing (supporting).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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