Recently, an anomalous behavior of the sub-threshold swing (SS), not adhering to Boltzmann limits and saturating below a certain critical temperature, has been observed in MOSFETs. In this work, we consider ultra-thin channel double-gate Silicon-on-Insulator (SOI) MOSFETs, where particularly at low device temperatures (T < 50 K), we illustrate the impact of Quantum Confinement Effects (QCEs) in enhancing the Source-to-Drain Tunneling (SDT) currents, thus resulting in these SDT currents significantly degrading the sub-threshold swing behavior. With reducing SOI channel thickness, where QCEs become more significant, we first show a non-linear increase in SS (degradation of SS, with increasing device temperatures), at low device temperatures, for shorter channel lengths, which then results in the saturation of SS for intermediate channel lengths, until eventually attaining SS values closer to the Boltzmann limit for longer channels, when SDT has become comparable to, or reduced below, the thermionic currents. The simulation approach presented in this work makes it possible to estimate the impact of QCEs on SDT accurately, through which the SS behavior at varying device temperatures (T = 15–150 K) can be theoretically explained for nanoscale MOSFETs.

Topics
Electronic band structure, Quantum confinement, Field effect transistors, Current-voltage characteristic, Silicon-on-insulator, Electrostatics, Cryogenics, Quantum tunneling
BT

band tail

DG

double gate

EMA

effective mass approximation

N(Ex)

supply function

NEGF

non-equilibrium Green’s function

QCE

quantum confinement effect

SCE

short channel effect

SDT

source-to-drain tunneling

SS

sub-threshold swing

TB

tight-binding

Tp(Ex)

tunneling probability

Tsi, Lg

silicon thickness, gate length

UTB SOI

ultra-thin-body silicon-on-insulator

Cryogenic CMOS has become a promising candidate for quantum computing1 and space applications.2–4 In this context, it is important to accurately predict MOS transistor behavior, wherein significant deviations are seen between theoretical expectations and experimental results.5,6 A case in point is the sub-threshold swing (SS), which determines the rate of transition of the drain current from the OFF-state to the ON-state, where unexpected saturation has been experimentally observed below a critical device temperature.7–9 

These experimental results have been explained in recent literature through exponentially decaying band tail states in the bandgap10–15 or through the impact of source-to-drain tunneling (SDT) current16–18 or through a combination of both.19–21 In these studies, attempts have been made to align simulations with experimental results by attributing the above-mentioned effects as being the reason for the anomalous SS behavior at low device temperatures. To explain this behavior of SS, the work done by Beckers et al. proposes physics-based models for the sub-threshold swing (SS) and threshold voltage (Vth), including incomplete ionization and temperature-dependent interface trapping, which is derived using a simplified EKV model in Refs. 22–27 by characterizing the commercial 28-nm bulk CMOS technology operating from room to cryogenic temperatures. One of the first reports citing the presence of band-tails to explain SS saturation at low-temperatures was by Bohuslavskyi et al.,12 which demonstrated that an exponential band-tail state adhering to Fermi–Dirac statistics leads to saturation of SS at deep-cryogenic temperatures. These band tail states are seen below the conduction bands and above the valence bands, respectively, arising as a consequence of disorder, usually seen more predominantly in amorphous semiconductors compared to crystalline semiconductors.28 Thermal, structural, impurity, and/or compositional disorder can all lead to the formation of band tail states. The attribution of band tail states (which are non-idealities) to SS behavior in MOSFETs at low device temperatures has been largely driven through experimental observations. However, to develop a comprehensive understanding of device behavior at low temperatures, it is critical to develop an accurate simulation methodology that takes physical effects into account while neglecting non-idealities.

Given the significant performance improvements that can be achieved by nanoscale MOSFETs,29 it is important to analyze the applicability of these devices for cryogenic CMOS applications. For these devices, it is important to clearly identify the important physical phenomena that are likely to manifest at low temperatures and have an effect on device performance metrics, such as sub-threshold swing (SS). This analysis of the performance of nanoscale MOSFET structures, such as Ultra-Thin-Body (UTB) Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs, is only likely to be possible through developing accurate simulation methodologies capable of taking important physical effects into account in an accurate and computationally efficient manner. Through such methodologies, it becomes possible to quantify the impact of Quantum Confinement Effects (QCEs) on device performance while considering a wide range of channel lengths and also accounting for phenomena such as source-to-drain tunneling reported to manifest in ultra-short channel MOSFETs at room temperature, but whose impact at lower device temperatures can only be clearly analyzed through an accurate simulation methodology. While there have been reports in the literature of SDT17,18 resulting in SS saturation at lower device temperatures, the precise quantification of SDT and the identification of a range of channel lengths where SDT effects have a significant impact on device performance have proven to be complicated.

In the literature, the effect of SDT on the saturation of SS at lower device temperatures has been analyzed by determining the total drain current through NEGF simulations by considering these effects through the relatively simplistic parabolic effective mass approximation (EMA).16,17 The NEGF simulation-based investigations suggest that SDT as a phenomenon is negligible beyond a channel length of 40 nm.16–18 In addition, based on these NEGF simulations, a model for SDT has also been proposed with a view to predict its effect on SS, where a parabolic source/channel barrier was assumed,20 which might be generally valid only at shorter channel lengths. However, the NEGF simulations, which have been the basis of all efforts to determine SDT, do not scale well with increasing channel lengths and have generally not been applied at higher channel lengths. It may be noted that the EMA approach, which has often been used in NEGF simulations, tends to consider Quantum Confinement Effects (QCEs) by making a parabolic approximation of the band structure, which results in EMA not being very accurate either where strong QCEs are seen [channel thickness is below the excitonic Bohr radius (aB) of silicon] or at low gate voltages30 (below the threshold voltage of the DG SOI MOSFET), where the impact of SDT is most prominently seen and is expected to impact SS. Therefore, in this work, we propose to determine the 1D band structure accurately through the Tight-Binding Method (TBM), through which the channel electrostatics are determined from the self-consistent solution of this band structure with the 2D Poisson’s equation. Now, using the Tsu–Esaki formalism, the constituents of the total drain current, including the SDT and thermionic components (while considering phonon scattering), can be quantified, over a wide range of device parameters.

The rest of this paper is organized as follows: In Sec. II, we discussed the band structure-based simulation approach to determine the SDT and thermionic currents for a wide range of channel lengths, SOI channel thicknesses, and device temperatures. Based on this simulation approach, the results obtained for the drain current are validated with experiment and other atomistic approaches in Sec. III. The behavior of the sub-threshold swing, particularly at lower device temperatures, is discussed through an analysis of the supply function and tunneling probability, highlighting the effect of SDT over an extended range of channel lengths, in Sec. IV, with a short conclusion then presented in Sec. V.

We begin this section by showing an approach to apply the tight-binding model for simulating the band structure and then show an algorithm to calculate the 2D channel electrostatics of UTB DG-MOS devices (as shown in Fig. 1) in an accurate and a computationally efficient manner by using the reduced band structure-based approach.31 To consider Quantum Confinement Effects (QCEs), which become extremely essential to consider, in UTB DG SOI MOSFETs, the sp3d5s* tight-binding (TB) model has been used to obtain the full band structure of the thin semiconductor channel.32,33 The TB fitting parameters for Si given by Jancu et al. are used at 0 K,34 and those given by Tan et al.35 are used at 300 K. The overlap matrix elements are expressed in terms of Slater–Koster two-center energy integrals or hopping integrals,36 which are obtained from the work by Rahman et al.37 (See the supplementary material for Hamiltonian construction.) Incorporating a temperature-dependent bandgap correction term into the band structure obtained from the TB Hamiltonian, assembled at T = 0 K, the band structure of the channel material at any temperature between 0 and 300 K is computed20,38 as follows:
(1)
where α is a material constant defined by Varshni et al.38 and β is a parameter that is dependent on material and channel thicknesses and can be computed as shown in Ref. 20.
FIG. 1.
Schematic of (100) Si channel in an ultra-thin-body (UTB) double gate (DG) MOSFET, where “z” corresponds to the channel thickness and “x” corresponds to the channel transport directions, respectively.
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Schematic of (100) Si channel in an ultra-thin-body (UTB) double gate (DG) MOSFET, where “z” corresponds to the channel thickness and “x” corresponds to the channel transport directions, respectively.

FIG. 1.
Schematic of (100) Si channel in an ultra-thin-body (UTB) double gate (DG) MOSFET, where “z” corresponds to the channel thickness and “x” corresponds to the channel transport directions, respectively.
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Schematic of (100) Si channel in an ultra-thin-body (UTB) double gate (DG) MOSFET, where “z” corresponds to the channel thickness and “x” corresponds to the channel transport directions, respectively.

Close modal

After obtaining the temperature-dependent band structure, we solve the 1D Poisson equation self-consistently with the 1D band structure31,39,40 in a computationally efficient manner by selecting significant k-points, particularly around the band minima (for details, see the supplementary material). After selecting the significant k-points, gate capacitance is obtained using the model developed by Mishra et al.,41 which is benchmarked with C–V obtained through the experimentally reported gate capacitance for a double-gated FinFET structure42 at T = 300 K (see the supplementary material). This approach is extended to solve 2D channel electrostatics using the algorithm shown in Fig. 2 43(for details, see the supplementary material). Besides being practical even for longer channel lengths, this band structure-based approach enables accurate determination of the conduction band energies in the lateral direction (along the channel length), which is necessary to study the impact of SDT for different channel lengths (up to high nm range).

FIG. 2.
Algorithm to obtain the thermionic and SDT currents through the self-consistent solution of the 1D band structure with the 2D Poisson equation.
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Algorithm to obtain the thermionic and SDT currents through the self-consistent solution of the 1D band structure with the 2D Poisson equation.

FIG. 2.
Algorithm to obtain the thermionic and SDT currents through the self-consistent solution of the 1D band structure with the 2D Poisson equation.
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Algorithm to obtain the thermionic and SDT currents through the self-consistent solution of the 1D band structure with the 2D Poisson equation.

Close modal

Having obtained the 2D electrostatic potential and the 2D conduction band energy profile, the location and energy corresponding to the top of the barrier (Etob) are obtained for different monolayers of a specific SOI channel. Based on the height and width of the source-channel barrier and the Etob identified for each monolayer, it becomes possible to determine the Source-to-Drain Tunneling (SDT) current density (obtained by considering energies from the bottom of the source-channel barrier to Etob) and the thermionic current density (obtained by considering energies from and above Etob) for each monolayer. For the calculation of tunneling probability, the WKB approach is used.44 

The tunneling probability can be obtained as follows:
(2)
where k(x) is the x-directed (direction of carrier transport) wave number and is obtained using the following equation:
(3)
The turning points xL and xR are obtained such that qV(x) > E, resulting in a real value of the wave number in the lateral distance, and meff is the effective mass in the tunneling direction with Planck’s constant ℏ.44 This can be easily understood from Fig. 3.45 The net electron tunneling current density along the x-axis is calculated using the Tsu–Esaki tunneling formulation46 as follows:
(4)
where dNdEΔkxΔky is the 2D density of states, which can be determined from the band structure, and N(Ex) is the supply function, which is shown in the following equation:
(5)
where Fs(E) and Fd(E) are Fermi–Dirac probability at the source/channel and drain/channel junctions, respectively. The summation limits for thermionic current density is Etob to Emax, where no tunneling is observed. Emax is the product of the number of considered bands (n = 5 for Tsi = 2 nm and n = 10 for Tsi = 7 nm) and a significant number of k points calculated from the 1D band structure calculation,31 and Emin is the conduction band minima. On the other hand, the summation limits for tunneling current density is Emin (bottom of the source-channel barrier) to Etob. From the current density [J(z)], the total drain current is obtained through the summation of the total current density (determined on a monolayer by monolayer basis) as follows:
(6)
This current is shown in  Appendix A, for Vds = 1 V (see Fig. 9). The total drain current can be considered as being the result of the thermionic and SDT currents, respectively, shown in Fig. 9.
FIG. 3.
Schematic of tunneling phenomenon for an arbitrary potential barrier showing the determination of the Source-to-Drain Tunneling (SDT) current as well as the thermionic current.
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Schematic of tunneling phenomenon for an arbitrary potential barrier showing the determination of the Source-to-Drain Tunneling (SDT) current as well as the thermionic current.

FIG. 3.
Schematic of tunneling phenomenon for an arbitrary potential barrier showing the determination of the Source-to-Drain Tunneling (SDT) current as well as the thermionic current.
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Schematic of tunneling phenomenon for an arbitrary potential barrier showing the determination of the Source-to-Drain Tunneling (SDT) current as well as the thermionic current.

Close modal

The total drain current obtained from our simulation approach is now validated through comparisons with experimental device data,11 shown in Fig. 4(a), at a cryogenic temperature (T = 10 K). The experimental device was fabricated using the 22 nm UTBB CMOS process with a top oxide thickness (EOT) of 1 nm and gate length of 18 nm, where the channel thickness for this device was 6 nm. By using similar device dimensions and temperature as the experimental device, we have compared the input characteristics at Vds = 0.8 V of our simulation with the experimental device, showing good agreement in terms of sub-threshold swing and weak inversion current, with slight deviation seen between the simulated results and the experimental results in the ON-state, primarily because the two devices are not exactly identical, with the experimental device having a back oxide (BOX) that is 25 nm thick. Through Fig. 4(b), we have also compared the I–V behavior (input transfer characteristics) obtained through our simulation methodology (Tsi = 2 nm; Lg = 14 nm) with a Si nanowire structure (Lg = 10 nm),17 which also shows reasonably good agreement, further validating our approach for a wide range of temperatures. Furthermore, we compare the input transfer characteristics obtained from the simulation approach presented in this work with the NEGF compact model45 and with experimental data,47 at T = 300 K, where we see reasonably good agreement, which validates our work for ultra-thin (UT) and relatively thicker SOI channels over a wide range of channel lengths (see the supplementary material).

FIG. 4.
Comparison of the I–V characteristics obtained through (a) this work (Lg = 18 nm) with experimental I–V characteristics for an 18 nm UTBB n-FET measured at 10 K,11 Vds = 0.8 V, T = 10 K. Comparison of the I–V characteristics obtained through (b) this work (Lg = 14 nm) with I–V characteristics obtained for a silicon nanowire (Lg = 10 nm),17 Vds = 0.1 V, T = 77 K.
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Comparison of the I–V characteristics obtained through (a) this work (Lg = 18 nm) with experimental I–V characteristics for an 18 nm UTBB n-FET measured at 10 K,11  Vds = 0.8 V, T = 10 K. Comparison of the I–V characteristics obtained through (b) this work (Lg = 14 nm) with I–V characteristics obtained for a silicon nanowire (Lg = 10 nm),17  Vds = 0.1 V, T = 77 K.

FIG. 4.
Comparison of the I–V characteristics obtained through (a) this work (Lg = 18 nm) with experimental I–V characteristics for an 18 nm UTBB n-FET measured at 10 K,11 Vds = 0.8 V, T = 10 K. Comparison of the I–V characteristics obtained through (b) this work (Lg = 14 nm) with I–V characteristics obtained for a silicon nanowire (Lg = 10 nm),17 Vds = 0.1 V, T = 77 K.
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Comparison of the I–V characteristics obtained through (a) this work (Lg = 18 nm) with experimental I–V characteristics for an 18 nm UTBB n-FET measured at 10 K,11  Vds = 0.8 V, T = 10 K. Comparison of the I–V characteristics obtained through (b) this work (Lg = 14 nm) with I–V characteristics obtained for a silicon nanowire (Lg = 10 nm),17  Vds = 0.1 V, T = 77 K.

Close modal

Having validated the drain current obtained using the simulation approach presented, we now determine the sub-threshold swing at different channel lengths, channel thicknesses, and device temperatures. These results are shown in Fig. 5. In this figure, we show that QCEs tend to exacerbate the effects of SDT. In other words, for a channel thickness of 2 nm, where strong QCEs are seen, the effects of SDT are much more significant, with the thermionic current being reduced (see  Appendix B). On the other hand, for a channel thickness of 7 nm, where QCEs have considerably receded, the thermionic current increases and is relatively more significant compared to the thermionic current component for a channel thickness of 2 nm, resulting in the SDT component having a more significant effect at a channel thickness of 2 nm compared to a channel thickness of 7 nm (see  Appendix B, where the channel lengths considered are kept identical to enable a more appropriate comparison). This results in SDT impacting the sub-threshold swing (SS), causing the SS to behave non-linearly at shorter channel lengths at lower device temperatures, while saturating at intermediate channel lengths, eventually resulting in adherence to Boltzmann temperature scaling when SDT has significantly receded [see Fig. 5(a)]. Due to the thermionic current being highly suppressed, the range of channel lengths, over which SDT has significance, is found to be much wider for a channel thickness of 2 nm [see Fig. 5(a)], compared to a channel thickness of 7 nm [see Fig. 5(b)], where the thermionic current component is more significant. As the channel thickness is increased further to 10 nm, where QCEs are further suppressed, the thermionic current component increases further and the range of channel lengths over which the SDT current component has relative significance decreases even further compared to 7 nm (see Fig. 6).

FIG. 5.
Average SS behavior, as a function of device temperature (15–150 K), at various channel lengths with (a) channel thicknesses of Tsi = 2 nm and (b) Tsi = 7 nm, Vds = 1 V, and Tox = 1 nm.
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Average SS behavior, as a function of device temperature (15–150 K), at various channel lengths with (a) channel thicknesses of Tsi = 2 nm and (b) Tsi = 7 nm, Vds = 1 V, and Tox = 1 nm.

FIG. 5.
Average SS behavior, as a function of device temperature (15–150 K), at various channel lengths with (a) channel thicknesses of Tsi = 2 nm and (b) Tsi = 7 nm, Vds = 1 V, and Tox = 1 nm.
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Average SS behavior, as a function of device temperature (15–150 K), at various channel lengths with (a) channel thicknesses of Tsi = 2 nm and (b) Tsi = 7 nm, Vds = 1 V, and Tox = 1 nm.

Close modal
FIG. 6.
Comparison of the sub-threshold swing behavior as a function of temperature, considering the variation of channel length, for Tsi = 7 and 10 nm, in the temperature range of 15–50 K. The reduced range of temperature considered in this comparison is to better illustrate the differing effects of quantum confinement between Tsi of 7 and 10 nm.
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Comparison of the sub-threshold swing behavior as a function of temperature, considering the variation of channel length, for Tsi = 7 and 10 nm, in the temperature range of 15–50 K. The reduced range of temperature considered in this comparison is to better illustrate the differing effects of quantum confinement between Tsi of 7 and 10 nm.

FIG. 6.
Comparison of the sub-threshold swing behavior as a function of temperature, considering the variation of channel length, for Tsi = 7 and 10 nm, in the temperature range of 15–50 K. The reduced range of temperature considered in this comparison is to better illustrate the differing effects of quantum confinement between Tsi of 7 and 10 nm.
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Comparison of the sub-threshold swing behavior as a function of temperature, considering the variation of channel length, for Tsi = 7 and 10 nm, in the temperature range of 15–50 K. The reduced range of temperature considered in this comparison is to better illustrate the differing effects of quantum confinement between Tsi of 7 and 10 nm.

Close modal

To explain these observations more clearly, we consider the case of Tsi = 2 nm as an example, where we first attempt to analyze the SDT phenomenon and the factors that contribute to it. This includes the supply function [N(Ex)] and the tunneling probability [Tp(Ex)], each of which is likely to have an impact on the contribution of SDT to the total drain current and hence the SS obtained (shown in Fig. 5). The effect of temperature is seen in terms of its impact on the supply function, as the number of carriers (electrons for an n-channel device) available to tunnel is dependent on the separation of the energy levels occupied by the carriers to the Fermi-energy level. In addition, at lower temperatures, only the energy levels very close to the Fermi-energy level will have any electron population. As a result, the supply function is temperature dependent (channel length independent), with the maximum supply function seen more at the center of the SOI channel [see Fig. 7(a)], while the tunneling probability is independent of device temperature [channel length dependent; see Fig. 7(b)]. It is the product of the supply function and the tunneling probability that helps determine the SDT current. We describe the phenomena that are manifesting in terms of the following salient points:

  • For very small channel lengths (Lg = 9 nm, where the thermionic current is completely insignificant when compared with the SDT current), the supply function and the tunneling probability are both quite significant and quantitatively comparable. It may be noted here that the supply function is dependent on device temperature but independent of channel length, while on the other hand, the tunneling probability is independent of device temperature but dependent on the channel length (see Fig. 7). As a result, when both quantities are comparable, the product of the two, which impacts the SDT current, tends to be more temperature sensitive like the supply function. This is seen in terms of the non-linear rise in SS over the temperature range of 15–50 K. This continues to manifest, as long as the supply function and the tunneling probability remain quantitatively comparable, even as the channel length rises, as seen in Fig. 5(a).

  • With increasing channel length (Lg > 18 nm, where the thermionic current continues to be much lesser than the SDT current), the nature of the source-channel barrier tends to change, becoming more trapezoidal, as a result of which the tunneling probability decreases substantially, while the supply function remains unchanged. As a result of this, the product of these two quantities decreases significantly and tends to be more influenced by the nature of the tunneling probability, which is temperature independent, as seen commencing from Lg = 18 nm, but more prominently from Lg = 27 nm. This phenomenon continues to manifest up to a channel length of 93 nm, resulting in SS saturating over a range of device temperatures from 15 to 50 K, as also seen in Fig. 5(a).

  • With a further increase in channel length (Lg > 186 nm, where the SDT current is now comparable to the thermionic current), the tunneling probability, which was significantly reducing with an increase in channel length, has reduced such that the product of the supply function and the tunneling probability, instrumental in determining the SDT current, has decreased to the extent that it now becomes comparable and begins to reduce below the thermionic current, as a result of which the SS begins to rise linearly with device temperature, over the entire range of device temperatures, following Boltzmann temperature scaling [see Fig. 5(a)].

  • As the channel thickness increases, for a specific channel length, the LgTsi ratio decreases, which implies that the source-channel barrier will continue to show more parabolic behavior over a wider range of channel lengths, resulting in increased quantitative significance of both the supply function and tunneling probability over a wider range of channel lengths [see Figs. 5(b) and 6], implying that the SDT behaves more like the supply function (greater temperature dependence). This is expected to result in a non-linear increase in SS with increasing device temperature from 15 to 50 K. This also means that the trapezoidal source-channel barrier, where the tunneling probability decreases significantly and thus reduces the SDT current, making it less temperature dependent, will now be seen at longer channel lengths with increasing SOI channel thicknesses.

FIG. 7.
(a) Supply function and (b) normalized ground state tunneling probability as a function of channel depth (along the “z” direction) at various gate lengths and temperatures, when Tsi = 2 nm.
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(a) Supply function and (b) normalized ground state tunneling probability as a function of channel depth (along the “z” direction) at various gate lengths and temperatures, when Tsi = 2 nm.

FIG. 7.
(a) Supply function and (b) normalized ground state tunneling probability as a function of channel depth (along the “z” direction) at various gate lengths and temperatures, when Tsi = 2 nm.
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(a) Supply function and (b) normalized ground state tunneling probability as a function of channel depth (along the “z” direction) at various gate lengths and temperatures, when Tsi = 2 nm.

Close modal

Finally, in Fig. 8, we show a comparison of the SS results obtained using the band structure-based approach with simulation and experimental results, shown in the literature, for various nanoscale MOSFET architectures. Through this comparison, we aim to show that the simulation approach presented in this paper has indeed taken QCEs and low temperature effects into account accurately. It is interesting to note that as opposed to many of the simulation works,18,19 where the SS was predicted to saturate even at shorter channel lengths, we show a non-linear rise in SS values with an increase in device temperature (between 15 and 50 K) at shorter channel lengths, which qualitatively appears to agree well with the SS obtained in a nanowire FET (where QCEs are most prominent), clearly indicating that the simulation approach presented in this work is able to accurately account for QCEs. Therefore, through the results presented, we have shown the dominance of the SDT effect in determining SS behavior at low device temperatures at channel lengths less than 100 nm.

FIG. 8.
Comparison of sub-threshold swing obtained from the simulation approach presented in this work with the model presented by Beckers10 (28-nm bulk CMOS process), various simulation works18,19 in the literature, and experimental data.7–9
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Comparison of sub-threshold swing obtained from the simulation approach presented in this work with the model presented by Beckers10 (28-nm bulk CMOS process), various simulation works18,19 in the literature, and experimental data.7–9 

FIG. 8.
Comparison of sub-threshold swing obtained from the simulation approach presented in this work with the model presented by Beckers10 (28-nm bulk CMOS process), various simulation works18,19 in the literature, and experimental data.7–9
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Comparison of sub-threshold swing obtained from the simulation approach presented in this work with the model presented by Beckers10 (28-nm bulk CMOS process), various simulation works18,19 in the literature, and experimental data.7–9 

Close modal

In this work, we simulated a UTB SOI DG MOSFET for a wide range of channel lengths at low temperatures, which are relevant for quantum computing applications. We discussed the band structure-based simulation approach to determine the accurate SDT and thermionic currents for various channel lengths, SOI channel thicknesses, and device temperatures. We have highlighted the importance of QCEs, underscoring the need to consider them accurately in determining channel electrostatics, where we show the non-linear and saturated behavior of the sub-threshold swing for a prolonged range of channel lengths, especially where we see significant QCEs. This limits the suitability of MOSFETs at shorter channel lengths for ultra-low power applications in quantum computing and also highlights areas for further improvement to meet the demands of such applications. It is therefore important to identify suitable channel materials, which are likely to ensure steeper SS behavior with increasing device temperature to ensure the usability of cryo-CMOS technology for quantum computing applications.

See the supplementary material S1 for assembly of Hamiltonian, supplementary material S2 for bandgap correction model, supplementary material S3 for selecting significant k points, supplementary material S4 for obtaining electrostatics, supplementary material S5 for benchmarking with experiment at 300 K, supplementary material S6 for extension to 2D channel electrostatics, and supplementary material S7 for comparisons.

We acknowledge financial support from the Science and Engineering Research Board (SERB), Department of Science and Technology (DST), under Grant No. CRG/2022/003217. N. V. Mishra acknowledges the Ministry of Education for support from the Prime Minister’s Research Fellowship (PMRF ID 0401551).

The authors have no conflicts to disclose.

All authors have equally contributed to this work.

Nalin Vilochan Mishra: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Software (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Aditya Sankar Medury: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Software (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

The data that support the findings of this study are available within the article.

From the current density (J(z)), as shown in Eq. (4), the total drain current is obtained [using Eq. (6)]. This current is shown in Fig. 9, for Vds = 1 V for various channel lengths at T = 15 and 50 K for Tsi = 2 and 7 nm. The sub-threshold swing can then be determined using the total drain current, the summation of thermionic and SDT currents shown in Sec. IV of this paper.

FIG. 9.
Input I–V characteristics for Tsi = 2 nm, with (a) Lg of 9 and 27 nm and (b) Lg of 186 nm; for Tsi = 7 nm, with (c) Lg of 35 and 43 nm and (d) Lg of 93 nm, at temperatures of 15 and 50 K.
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Input I–V characteristics for Tsi = 2 nm, with (a) Lg of 9 and 27 nm and (b) Lg of 186 nm; for Tsi = 7 nm, with (c) Lg of 35 and 43 nm and (d) Lg of 93 nm, at temperatures of 15 and 50 K.

FIG. 9.
Input I–V characteristics for Tsi = 2 nm, with (a) Lg of 9 and 27 nm and (b) Lg of 186 nm; for Tsi = 7 nm, with (c) Lg of 35 and 43 nm and (d) Lg of 93 nm, at temperatures of 15 and 50 K.
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Input I–V characteristics for Tsi = 2 nm, with (a) Lg of 9 and 27 nm and (b) Lg of 186 nm; for Tsi = 7 nm, with (c) Lg of 35 and 43 nm and (d) Lg of 93 nm, at temperatures of 15 and 50 K.

Close modal

With increasing Vds, for a specific channel length, the thermionic current is found to increase substantially, while the SDT current also increases slightly, thus resulting in the ratio of the SDT current to the thermionic current decreasing with increasing Vds as seen from Fig. 10.

FIG. 10.
Ratio of SDT current to thermionic current at device temperatures of 15 and 50 K for (a) Tsi = 2 nm and (b) Tsi = 7 nm, with the same physical channel length of 9 nm.
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Ratio of SDT current to thermionic current at device temperatures of 15 and 50 K for (a) Tsi = 2 nm and (b) Tsi = 7 nm, with the same physical channel length of 9 nm.

FIG. 10.
Ratio of SDT current to thermionic current at device temperatures of 15 and 50 K for (a) Tsi = 2 nm and (b) Tsi = 7 nm, with the same physical channel length of 9 nm.
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Ratio of SDT current to thermionic current at device temperatures of 15 and 50 K for (a) Tsi = 2 nm and (b) Tsi = 7 nm, with the same physical channel length of 9 nm.

Close modal
1.
F.
Jazaeri
,
A.
Beckers
,
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