Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

A bilayer tunneling field effect transistor (TFET) with gate-normal band-to-band tunneling (BTBT) is one of ideal device structures to realize extremely-small subthreshold swing (S.S.) because overlap of the density of states (DOS) between the source and the channel, inducing the BTBT current, can be directly modulated over the entire region of the tunneling junction by the gate voltage (V_g).^1–5 Additionally, the large on-state current (I_on) is expected in the bilayer TFETs thanks to the larger tunneling area and the shorter tunneling distance which is controlled by the thickness of the upper channel layer. On the other hand, type-II energy band alignment, which has the higher valence band maximum in the source region and the lower conduction band minimum in the channel region for n-channel TFETs, is promising to enhance the BTBT probability because of reduction in the effective barrier height (E_b-eff) and the resulting shorter tunneling distance.^5–10 As a result, a combination of these two approaches, bilayer TFETs composed of source and channel materials with type-II energy band alignment, is one of the most effective structures for satisfying both high performance and extremely-steep S.S. In reality, however, there are several difficult challenges for fabricating these devices because of the structural complexity.^3,4 Also, in drawing out the tunneling current from the tunneling junction to the drain contact, non-ideal leakage currents near the drain edge induced by the concentration of the electrical field tend to significantly deteriorate the off currents (I_off) and the S.S. properties.^11,12

In order to overcome these obstacles, we have recently proposed a new bilayer TFET structure by utilizing a hetero tunneling junction composed of an n-type oxide-semiconductor (n-OS) and a p-type group-IV-semiconductor (p-IV).¹³ Figure 1(a) illustrates the concept of this bilayer TFET structure and its energy band diagram normal to the gate/high-k/n-OS/p-IV tunneling junction under (b) off-state and (c) on-state. When positive voltage (V_g) is applied to the gate electrode formed on the n-OS side, DOS of the valence band in the p-IV source region is overlapped with that of conduction band in the n-OS channel region overlaps, leading to the generation of BTBT at the tunneling junction. This proposed tunneling junction has several attractive features as follows; (I) The proposed material combination allows us to provide the type-II energy band structure with the small effective barrier height (E_b-eff = E_c-OS − E_v-IV, where E_c-OS is the conduction band minimum of n-OS and E_v-IV is the valence band maximum of p-IV) under the semiconductors with relatively large bandgap (E_g), which keep small I_off. Furthermore, this E_b-eff value is tunable by changing the material combination and these compositions, as shown in Fig. 1(d).^14–16 (II) OS materials having the conduction band minimum at the Γ point allows direct tunneling, which is in contrast with typical group-IV semiconductors which do not have the conduction band minimum at the Γ point.¹⁷ This tunneling path is effective for realizing high tunneling probability.^18,19 (III) The nature of n-type carrier conduction in OS layers can realize the junction-less channel structure, where additional n-type doping is not needed in the gate-underlap region. This junction-less structures as well as the large bandgap of OS can effectively suppress any non-ideal leakage current near the drain edge. (IV) The simple device structure and the fabrication processes by utilizing well-developed deposition techniques of OS layers can lead to high compatibility to the CMOS platform with a large-size Si substrate. As a result, we can expect to realize high performance bilayer TFETs with high I_on and small S.S. on the Si CMOS platform.

Therefore, in this study, we investigate the potential of the proposed bilayer TFET with type-II hetero tunneling junction as a high-performance TFET based on technology computer aided design (TCAD) simulation.²⁰ Here, an n-ZnO/p-Ge bilayer TFET is mainly examined because this structure can provide smaller E_b-eff by utilizing a realistic material combination. In particular, ZnO or ZnO-based oxide semiconductors have been well-studied. The high electron mobilities have already been reported everywhere^21–25 including our previous work,²⁶ even in the poly-crystalline layers. Also, we examine influences of principal device parameters such as E_b-eff by using a SiGe source and other OS materials, and channel layer thickness on the electrical performance of the proposed bilayer TFET for clear guideline of the device design. Then, we investigate the influences of the non-uniformities of the tunneling junction such as the channel thickness and surface potential at the high-k/OS interface, which could be other key factors for the actual device fabrications with drawing out the attractive potential of the proposed TFET.

First, the ideal performance of the proposed n-OS/p-IV bilayer TFET is investigated by using TCAD simulation based on Synopsys Sentaurus simulator with non-local BTBT model.¹⁷ Figures 2(a) and 2(b) show the device structure used in the simulation and the simulated 2-dimensional (2D) distribution of the BTBT rate near the n-OS/p-IV hetero tunneling junction, respectively. The red color in Fig. 2(b) indicates the amount of the BTBT rate in logarithmic scale. Here, as the material parameters of n-OS, those of bulk ZnO such as the relative permittivity of 8.8,^27–29 the electron affinity of 4.2 eV^13,30 and the electron/hole effective masses of 0.28m₀/0.59 m₀,^27,28,31 where m₀ is mass of a free electron, were used. The impurity concentrations in both n-type channel and p-type source regions were taken to be 3×10¹⁸ cm^–3. It is clearly seen that vertical tunneling from near the surface of the p-IV source to the top surface of the n-OS channel, that is high-k/n-OS interface, is uniformly generated by applying positive V_g. Figure 2(c), 2(d) and 2(e) show the energy band diagrams of n-Ge/p-Ge homo, n-ZnO/p-Ge hetero and n-ZnO/p-Si hetero tunneling junctions, respectively, in off- and on-states. Here, we assume the applied V_g values in the off- and the on-state as –5 mV and +0.5 V, respectively, from V_off, defined as V_g at I_d of 0.1 pA/μm in simulation. It can be seen that band bending in ZnO, Ge, and Si are different because of the difference of the permittivity. For example, in the n-ZnO/p-Ge hetero junction, the amount of band bending in the n-ZnO channel is much larger than that in the p-Ge source, owing to the lower permittivity of ZnO than Ge. In the n-ZnO/p-Si hetero junction, the difference in the amount of band bending between the n-ZnO channel and the p-Si source is smaller because of the smaller difference in the permittivity between ZnO and Si, though that of n-ZnO is still larger than that of p-Si. Additionally, the energy band of the n-ZnO/p-Ge hetero junction is almost flat under its off-state condition thanks to the small E_b-eff. On the other hand, the energy band of the n-ZnO/p-Si hetero junction is already bent even in its off-state because the n-ZnO/p-Si junction forms a long depletion region in the p-Si source due to the large E_b-eff between ZnO and Si. The large permittivity difference and the small E_b-eff in the n-ZnO/p-Ge is effective to reduce the tunneling distance and resulting increase in the BTBT probability.

Figure 3(a) shows I_d-V_g characteristics of these three TFETs with the lateral junction length (L_g) of 100 nm and equivalent oxide thickness (EOT) of 1 nm. It is found that the n-ZnO/p-Ge hetero-junction can enhance I_on by more than 2 orders than the n-Ge/p-Ge homo-junction thanks to the smaller E_b-eff and the shorter tunneling distance, as explained in the energy band diagram in Fig. 2. On the other hand, I_on of n-ZnO/p-Si TFET is not sufficiently high, although it works as a bilayer TFET as predicted from Fig. 2. It is found that the on/off switching of the bilayer TFETs is extremely steep and that the minimum S.S. value is as small as 1 mV/dec. Also, the remarkably large I_on/I_off current ratio more than 8 orders is obtained. It is also observed, on the other hand, that the change in the I_d-V_g characteristics with applied V_d from 50 to 350 mV is largely different between the n-ZnO/p-Ge and n-ZnO/p-Ge devices. Figures 3(b) and 3(c) show I_d-V_d characteristics of the n-ZnO/p-Ge and the n-ZnO/p-Si TFET, respectively, and it is clearly observed that I_d-V_d characteristics of these TFETs are different each other. The typical linear and saturation regions are observed in the Ge TFET for small V_g, although I_d tends not to saturate with increasing V_d particularly for larger V_g. Furthermore, the I_d value as high as 100 μA/μm can be expected. In the Si device, on the other hand, the I_d-V_d curves show the Schottky-like non-ohmic characteristics.

Here, the Schottky-like non-ohmic I_d-V_d characteristic is often observed for various types of TFETs and some possible origins for this characteristic have been still discussed.³² Furthermore, in the bilayer TFET structure, uniformity of the BTBT probability over the channel under the gate electrode might be degraded with non-uniform band bending along the source-drain direction after applying V_d. Therefore, the profiles of E_c-OS along the source-drain direction is simulated, in order to examine the uniformity of the energy band bending with V_g and V_d, which directly changes the BTBT rate. Figures 4(a) and 4(b) show the profiles of E_c-OS at the most ZnO channel surface (∼0.2 nm away from the high-k/ZnO interface) for the ZnO/Ge and ZnO/Si TFETs, respectively. Also, Figs. 4(c) and 4(d) show the 2D distributions of BTBT rate with low V_d of 50 mV and high V_d of 300 mV, respectively. Here, V_g swing is defined as V_g - V_off. It is clearly observed that E_c-OS is almost uniform along the source-to-drain direction in any bias conditions, except for in the gate edge regions. Additionally, it can be clearly confirmed that uniformity of BTBT at the tunneling junction along the source-to-drain direction is not degraded even with high V_d of 300 mV. On the other hand, E_c-OS at the ZnO channel surface is largely modulated by V_d, which increases the potential drop at the high-k/ZnO interface and the resulting BTBT rate. This is because the electrical conduction in the ZnO channel is much higher than that through the tunneling junction, which can be an origin of the continuous increase in I_d with V_d, shown in Figs. 3(b) and 3(c).

Also, the change in E_c-OS and the increase in the BTBT rate with increasing V_d are more significant for the ZnO/Si TFET than for the ZnO/Ge TFET. The remarkably large moderation of the energy band of the ZnO/Si TFET caused with V_d (not with V_g) can lead to the non-ohmic I_d-V_d characteristic. Here, when we compare the I_d-V_d characteristics between ZnO/Ge and ZnO/Si TFETs under same E_b-eff given by the intentional adjustment of the E_c-OS position, the Schottky-like I_d-V_d characteristic has been still observed in the ZnO/Si TFET (not shown). This result indicates that the difference in the I_d-V_d characteristics between ZnO/Ge and ZnO/Si TFETs is attributable to that in the material parameters such as permittivity between p-Si and p-Ge, which can modulate the voltages across the ZnO channel and the source region under a give V_g value.

The tunability of the band lineup of the n-OS and p-IV hetero tunneling junction is one of the advantages of the present TFET structures. Here, the E_c-OS position can be changed by the nature of the n-OS materials and the E_v-IV position can be continuingly optimized by the Ge fraction in the SiGe source. I_on is calculated as a function of the Ge fraction in the SiGe source for various E_c-OS values in order to understand the impact of E_b-eff on I_on. The results are shown in Fig. 5(a). Here, I_on is defined as the I_d value at V_g = V_off + 0.3 V, where I_off is fixed to be 1 pA/μm. The material parameters of ZnO are still used for those of the OS channel except E_c-OS, which is intentionally changed from 4.0 to 4.8 eV. The I_on values exponentially increase with decreasing E_c-OS and increasing the Ge fraction. In particular, it is found that a slight change of E_v-IV by using Si_0.7Ge_0.3, commonly used in advanced Si technologies, significantly enhances I_on in comparison with Si. Also, I_on tends to saturate in high Ge content and large E_c-OS regions. This saturation is attributable to the parasitic resistance of the gate-underlapped OS region between the tunneling junction and the drain electrode. Figures 5(b) and 5(c) show minimum S.S. near I_d of 1 pA/μm and average S.S. over the V_g swing of 0.3 V, respectively, as a function of the Ge fraction for various E_c-OS values. Reduction of E_b-eff also improves the sub-threshold properties. The minimum and the average S.S. values of ∼1 mV/dec. and ∼40 mV/dec., respectively, can be obtained for small E_b-eff.

The choice of the thickness of the n-OS channel layer (t_OS) is also an important device design issue, because it directly changes the tunneling distance and the resulting tunneling probability. Figure 6(a) and 6(b) show the change in the I_d-V_g characteristics of the n-ZnO/p-Ge bilayer TFET with changing t_OS and the energy band profiles in the tunneling junction at a certain V_g of 0.6 V, respectively. Here, Ge is selected as the source material in this calculation to examine the influences of t_OS on high-performance devices with small E_b-eff. EOT and the channel length are taken to be 4 nm and 50 nm, respectively. Also, the carrier concentrations in the n-ZnO channel and the p-Ge source are assumed to be 3×10¹⁸ and 5×10¹⁸ cm⁻³, respectively. The shift of off-state voltage (V_off), defined as V_g at I_d of 0.1 pA/μm here, and the change in I_on are clearly observed with changing t_OS. Figures 7(a) and 7(b) summarize V_off and I_on at V_g swing of 0.3 V, respectively, as a function of t_OS for various EOT values. The V_off values shift toward a negative V_g side with increasing t_OS and this shift is more significant in thicker EOT. The threshold voltage for starting to generate BTBT in the TFET is determined by the energy position of E_c-OS at the ZnO channel surface, independent of t_OS. This fact means that the amount of the total potential drop across the Ge source and the ZnO channel under the threshold condition does not change with t_OS, although the electrical field across the ZnO/Ge tunneling junction decreases with increasing t_OS. At the same time, the electrical field through the gate insulator is also reduced with increasing t_OS. As a result, the V_off value decreases. On the other hand, I_on exponentially increases with thinner t_OS because of the shorter tunneling distance, while the EOT dependence of I_on is quite small. It is also found that S.S. is not degraded obviously by thicker or thinner channels. Here, the similar t_OS dependence has also been confirmed in n-OS/p-Si TFET (not shown).

As a result, it has been found from the TCAD simulation results that the bilayer TFETs composed of the n-OS/p-IV hetero-junction with the type-II energy band alignment have high potential for steep on-off switching with small V_g swing. In particular, the band profile at the hetero tunneling junction along the source-to-drain direction can be uniformly controlled by V_g, which is a promising feature of the bilayer TFETs to realize small S.S. Also, the bilayer TFET with E_b-eff typically lower than 0.4 V, which can be obtained by the Ge fraction higher than 70% and/or E_c-OS larger than 4.3 eV, are effective to achieve high I_on of ∼100 μA/μm, the I_on/I_off ratio higher than 8 orders and the small average S.S. of ∼40 mV/dec. under the supply voltage less than 0.3 V.

We have recently succeeded the experimental demonstration of the operation of the present bilayer TFETs fabricated by using an n-ZnO channel and a p-Si or a p-Ge source.¹³ However, the experimentally achieved S.S. value is much higher than the values predicted by TCAD simulation. Here, we have also observed the non-uniform channel thickness from cross sectional transmission electron microscope (TEM) images of the TiN/Al₂O₃/ZnO/Si tunneling junction after the crystallization of the ZnO layer.^13,26 Thus, this thickness fluctuation might be one of possible origins of the poor subthreshold properties of the experimental results. On the other hand, the stretch out of the I_d-V_g characteristics could also be caused by charge trapping/de-trapping related to interface states at the Al₂O₃/ZnO interface. Additionally, it is known that interface states created at oxide/semiconductor interfaces can cause the fluctuation of the potential at the semiconductor surfaces.³³ If the channel thickness and the surface potential are spatially fluctuated across a tunneling junction area, the energy band diagram must have the non-uniformity over the tunneling junction area, affecting the sub-threshold properties. Therefore, we investigate the influences of the channel thickness fluctuation (CTF), interface states and the surface potential fluctuation (SPF) at the high-k/OS interface on the degradation of the sub-threshold characteristics of the bilayer TFETs.

As found in Fig. 6, the threshold voltage of the n-OS/p-IV bilayer TFETs largely shifts with changing t_OS, while the sub-threshold characteristics are not degraded. However, if t_OS is fluctuated over a tunneling junction region of one device, the total I_d-V_g curves becomes less steep because of the summation of the multiple I_d-V_g curves with different threshold voltage. Such a degradation of the sub-threshold slope is schematically illustrated in Fig. 8(a). Actually, it has been observed from cross-sectional TEM images of the fabricated device that the thickness of the ZnO channel layer is not uniform.¹³ Figure 8(b) shows the height histogram of the ZnO surface reproduced from an atomic force microscope (AFM) image of a ZnO/Si hetero-structure before the gate oxide deposition. Since the ZnO/Si interface is much smoother than the ZnO layer surface, this roughness directly corresponds to the fluctuation of the thickness of the ZnO channel layer. The main portion of the histogram can be well fitted by the Gauss distribution with a standard deviation of (σ_t) of 0.58 nm, while the distribution has an additional tail in the larger height (thickness) side.

Figure 9 shows the calculated I_d-V_g characteristics of a ZnO/Ge TFET with the OS channel thickness fluctuation. The I_d value with the OS thickness fluctuation (I_d-TF) is calculated as follows,

where, i_d(t_OS, V_g) is the drain current of a TFET with uniform t_OS, and P(t_OS) is the probability of each t_OS. Here, P(t_OS) is assumed to be the height histogram obtained from the AFM result of Fig. 8(d). It is clearly found that the sub-threshold characteristics of the bilayer TFET is degraded by CTF. It is also observed from the comparison between the two CTF distributions, the fitted Gaussian distribution and the AFM histogram, that the tail of the fluctuation toward the thicker t_OS side leads to the further degradation of sub-threshold characteristic. As a result, I_on obtained by a certain V_g swing from V_off is significantly reduced due to the negative shift of V_off. Therefore, these results emphasize the necessity of improvement of the t_OS uniformity for the better performance with maximizing the merits of the bilayer TFETs. The detailed S.S. and I_on values degraded by CTF will be discussed later.

Generally, interface states at gate-oxide/semiconductor interfaces stretch out the I_d-V_g characteristics because of charge trapping and/or de-trapping associated with the surface potential change. Additionally, in bilayer tunneling FETs with potential fluctuation at the OS-channel surface, the energy band diagram in the tunneling junction along the gate metal direction is no longer uniform over a tunneling area, suggesting that the spatial non-uniformity of the tunneling probability might not be ignored, as shown in Fig. 10(a). Therefore, influences of interface states and the surface potential fluctuation due to trapped charges are examined independently.

The degradation of the I_d-V_g characteristic of the ZnO/Ge bilayer TFET due to charge trapping/de-trapping attributable to interface states is evaluated, first. Figure 10(b) shows the surface potential (Ψ_s-OS), which is the position of E_c-OS at the surface of the OS channel measured from the Fermi level, and I_d as a function of V_g corresponding to the on/off switching. Then, the I_d-V_g characteristics are calculated with assuming a uniform energy distribution of an interface state density (D_it) over the bandgap of ZnO and a V_g shift by the density of the trapped charges of ΔQ_it = qD_itΔΨ_s-OS, where q is the elementary charge. It is found in Fig. 10(b) that the change in Ψ_s-OS is extremely small in the sub-threshold region of this bilayer TFET. Figure 11(a) shows the calculated I_d-V_g characteristics including the influence of interface states. The sub-threshold characteristics are still extremely steep even with a large amount of D_it. This is because ΔΨ_s-OS in the sub-threshold region is very small and the amount of the trapped charges itself can be ignored. On the other hand, since the extremely high D_it of 10¹³ to 10¹⁴ cm^-2eV^-1 prevents the deep band bending of the surface potential in the on-state, I_on decreases with increasing D_it.

Subsequently, the influence of SPF on the TFET performance is examined. We have already obtained Ψ_s-OS and I_d as a function of V_g without taking the surface potential fluctuation into account, as shown in Fig. 10(b). In this study, by assuming the gauss distribution for the fluctuation of Ψ_s-OS, the I_d values with SPF (I_d-PF) at each V_g can be numerically calculated as follows.

Here, σ_s is the standard deviation of the surface potential. The values of σ_s are calculated on a basis of the Brews model given by the following equations,^33,34

where ε_s and ε_ox are the permittivity of a semiconductor and a gate insulator, respectively, C_ox and C_d are capacitances of a gate insulator and a semiconductor, respectively, N_cc is the charged center density, and λ is a parameter related to the surface potential fluctuation. Here, λ of 7.5 nm was used.³³ A capacitance associated with interface traps is not included in this equation. It should be noted here that positive voltage is applied to the gate metal to turn-on the proposed n-OS/p-IV TFETs, meaning that the OS channel surface is accumulated. Hence, in accumulation condition, σ_s is represented by using accumulation layer capacitance (C_acc) with quantum effect as follows.³⁴ 

where, h is Planck’s constant and m^* is the electron effective mass in OS channel (=0.28m₀). Figure 11(b) shows the influence of SPF on the I_d-V_g characteristics of the n-ZnO/p-Ge TFET with σ_s (×kT/q) of 5, 10, or 20 meV. Similar to the influences of CTF, V_off shifts toward the negative V_g side. This shift is caused by BTBT in the region with deeper E_c-OS, which has more negative V_off. As a result, the total I_d-V_g characteristic becomes less steep than that without SPF. The σ_s (×kT/q) values corresponding to N_cc of 1×10¹², 1×10¹³ and 1×10¹⁴ cm^–2 are estimated to be 3.2, 10, and 32 meV, respectively, under the accumulation condition of the OS channel surface. As a result, the influence of SPF on the performance of the present TFETs is expected not to be significant. More detailed results on the bilayer TFET performance with various σ_s such as I_on and average S.S. are described in the next section with an emphasis on the impact of EOT scaling.

Based on these simulation results, we can understand that influence of charge trapping/de-trapping in interface states at the gate-oxide/OS-channel interface is negligibly small, because the change in the surface potential of the OS channel in the sub-threshold region is extremely small. On the other hand, this fact means that a small variation of Ψ_s-OS by any mechanisms clearly shifts the threshold voltage. Therefore, if trapped charges at interface states can cause the spatial fluctuation of Ψ_s-OS, V_off can be shifted toward the negative V_g side and S.S. can be increased.

In the section II, we have shown that there is no clear impact of EOT on the sub-threshold properties of the TFET without any fluctuations.¹³ On the other hand, if the non-uniformities in the TFET are not negligible as discussed above, EOT can change the magnitude of the CTF/SPF influences. Figure 12(a) shows the degradation of the I_d-V_g characteristics of the ZnO/Ge bilayer TFETs caused by CTF for EOT of 1 or 4 nm. EOT scaling does not increase I_on drastically but it significantly suppresses the negative V_off shift caused by CTF, resulting in the better sub-threshold property. Figures 12(b) and (c) benchmark the impact of EOT scaling on average S.S. and I_on, respectively, of bilayer TFETs with CTF under a V_g swing of 0.1 or 0.3 V from V_off. In thicker EOT, the average S.S. increases and I_on decreases largely because of the CTF. Meanwhile, the average S.S. under small EOT hardly increases even under the same degree of CTF. Also, small EOT increases I_on under a certain V_g swing thanks to the suppression of the negative V_off shift.

Similarly, reduction of EOT can mitigate influences of SPF. Figure 13(a) shows the I_d-V_g characteristics of the bilayer TFET degraded by SPF for EOT of 1 or 4 nm. Figure 13(b) and (c) also plot the average S.S. and I_on, respectively, of the bilayer TFET under a V_g swing of 0.1 or 0.3 V, as a function of EOT. It is clearly found that both the smaller average S.S. and the higher I_on are achievable by thinning EOT even if the performance of the TFET is strongly affected by SPF.

As a result, it can be concluded that reduction of EOT as well as the improvement of the t_OS uniformity and the high-k/OS interfacial quality are important directions to improve the bilayer TFET performance. The influences of the non-uniformities of the OS thickness and the MOS interface charges are particularly important for the bilayer TFETs because the current is composed of the gate-normal BTBT current over the entire region of the tunneling junction, while a typical planar TFET structure utilizes BTBT only near the surface of the source/channel junction just below the gate electrode. Therefore, the improvements of the uniformities to suppress the performance degradation and EOT scaling to mitigate these influences are both the important guidelines for any kinds of bi-layer TFETs utilizing gate-normal BTBT.

In this study, we have proposed a new concept on a hetero tunneling junction with the type-II energy band alignment realized by an n-OS channel and a p-IV source and have addressed the effectiveness of a bilayer TFET employing this hetero tunneling junction with gate-normal BTBT. TCAD simulations have revealed the unique and remarkably high potential of the proposed bilayer TFET such as high I_on, larger I_on/I_off ratio, near-zero minimum S.S. and small average S.S. average. It has also been clarified that reduction of E_b-eff by the OS material selection and the Ge fraction in the SiGe source effectively increases I_on with decreasing S.S. and that t_OS is another key parameter to increase I_on. On the other hand, it has been found that non-uniformities associated with the tunneling junction thickness and the gate stack structure significantly degrade the sub-threshold properties of bilayer TFETs. The threshold V_g to generate BTBT, which varies with the channel thickness and the E_c-OS position at the OS channel surface, is negatively shifted in the I_d-V_g characteristics under the existence of CTF or SPF, which increases the S.S. value and decreases I_on at certain V_g swing from V_off. Thus, the improvement of the uniformities related to the tunneling junction is critical to the high performance of the bi-layer TFETs. It has been found, in addition, that thinning of EOT is effective to mitigate these influences. Therefore, not only the improvements of the uniformities but also thickness of gate insulator are important guidelines for bilayer TFETs with gate-normal BTBT.

This work was supported by JST (Japan Science and Technology Agency) CREST Grant Number JPMJCR1332, Japan.