Silicon based complementary metal-oxide-semiconductor field-effect-transistor (CMOSFET) technology has continued to progress unabated for last five decades despite various challenges arising due to extreme scaling. Pervasive use of Si technology is evident in a large spectrum of products ranging from high end mainframe and server computers for businesses to laptops, smartphones, and internet of things (IoT) for consumer-oriented products. There is an ever-increasing demand to improve Si device performance for the above described and future products. Strain engineering is one of the key aspects to improve transistor performance. In this review, we describe strain engineering in silicon based advanced CMOS technology, which has evolved from conventional two-dimensional (2D) MOSFET structure to 3D FinFET structure. The impact of shrinking dimensions of scaled FinFETs on channel strain engineering as well as options for strain engineering in future CMOS architecture are described. Finally, strain engineering in non-silicon based functional materials such as gallium nitride (GaN) and 2D materials will be briefly discussed.
Strain engineering refers to the mechanical deformation of a material for the purpose of improving one or more of its properties. In the case of semiconductor materials, the most popular application of strain manipulation is to improve carrier transport and therefore current drive in transistors. There has been a great deal of theoretical and experimental works performed in the field of carrier transport in strained semiconductors. A history of carrier mobility enhancement in 2D and 3D CMOS architectures by strain engineering is described in this section.
A. Strain engineering in conventional 2D CMOS
Although a pioneer work to enhance carrier mobility has been done in early 1980s,1 it was not until the late 1990’s that strained channels were viewed as requisite elements in CMOS technology. Initial work2 demonstrated electron mobility enhancement in bi-axially strained Si (below the critical thickness) on a relaxed SiGe virtual substrate with a larger lattice parameter than crystalline Si. The amount of (biaxial) tensile strain in the thin Si channel layer was varied by controlling the Ge content in the virtual substrate. Both electron1–10 and hole11–17 mobilities were shown to improve significantly (>30%) with increasing strain. The introduction of compressive uniaxial strain in the Si channel by embedding pseudomorphic SiGe in adjacent source-drain(S/D) regions has become the key enabler for improving transistor performance since its adoption in 90 nm CMOS technology node.18–21 On the other hand, introducing uniaxial strain by embedded S/D epitaxy in nFETs has been challenging because it requires an embedded pseudomorphic Si:C source-drain structure22,23 where the substitutional C doping of >1.5% is required. The latter doping level is orders of magnitude higher than allowable by the solid solubility limit of C in Si. This fundamental challenge was nevertheless overcome for a planar FETs at 22 nm node by an innovative sequential deposition/etching process at temperatures of <550° C which overcame the thermodynamic constraint.23 Embedded S/D Si:C epitaxy has not been implemented in 3D transistor architecture such as FinFET. This is due to unconstrained free surfaces introduced during the source-drain epitaxial growth. The main technique for introducing tensile strain in nFETs involves either process induced strain from a stress liner24–26 or stress memorization technique which stresses a gate material itself.27,28 It is also known that the carrier mobility sensitivity to the channel strain is affected by the channel surface orientation and the channel direction.29–33 Due to process simplicity and significant performance benefit of implementing strain techniques in CMOS, strain scaling has continued more than over last seven generations (since 90nm technology node) of CMOS products, especially in pFETs enabled by embedded SiGe process.
B. Strain engineering in 3D CMOS and its scaling impact
Channel strain engineering continues to play a prominent role for future CMOS technology however, to keep the same level of channel strain by embedded S/D SiGe is challenging as transistor dimension shrinks. This is because the volume of stressor (volume of SiGe in S/D region) reduces as transistor dimension shrinks. Figure 1 shows a trend of compressive channel strain by embedded SiGe as a function of a transistor gate pitch.34 Please note that S/D epitaxy volume depends on gate pitch, where the volume of embedded SiGe lowers as gate pitch shrunk. In order to overcome the strain deficiency in a tight gate pitch environment, compressively strained SiGe or Ge channel (rather than a Si channel) for pFETs has been explored,35–43 which is going to be discussed in the later sections of this review. Strain measurement in nanoscale structures require transmission electron microscope (TEM) based techniques. The resolution of conventional X-ray diffraction (XRD) is limited to its beam spot diameter of >1um which is orders of magnitude larger than required to measure strain in scaled 2D or 3D FETs. In modern TEMs beam diameter of ∼5nm can be routinely achieved which allows precise 2D mapping of channel strain even in the most aggressively scaled FET with a channel length of <20nm. The strain is measured by either a nanobeam diffraction (NBD) technique or a newly developed precession electron diffraction (PED) technique.44
II. STRAIN ENGINEERING IN SIGE FinFETS: FUNDAMENTAL MATERIAL STUDIES
Since epitaxial growth of Si and SiGe is an integral part of FET channel and source-drain formation, controlling the structural quality of these epitaxial layers is at the heart of strain engineering technology. Ideally, epitaxial layers should be free of defects to avoid strain relaxation, device reliability degradation, and anomalous dopant redistribution. Development of novel in situ surface cleans in the last decade has not only reduced crystallographic defects in epitaxial Si and SiGe layers but has also enabled their reproducibility in manufacturing environment. These developments have indeed resulted in higher product yield. The development of gas purifier technology which has been the backbone of achieving parts per trillion level pure oxygen and moisture-free gases should not be undermined. It is the combination of in situ chemical surface in conjunction with ultra-high purity gases that has allowed the CMOS industry to grow high structural quality Si and SiGe layers even at <600°C. Epitaxial growth at such low temperature may be pre-requisite for future CMOS technology nodes such as 5nm node and beyond.
A. Strain engineering enabler: In situ chemical clean and moisture–free gases for epitaxy
A crystallographic defect-free epitaxial growth process is paramount for strain engineering of a Si MOSFET since defects can relax the MOSFET channel and lower its performance. In addition, these defects are known to increase the reverse leakage current. It should be recognized that during fabrication of CMOS silicon under goes hundreds of process steps. Maintaining surface cleanliness during processing and in particular, right before epitaxial growth is critical to establish a robust and defect-free epi process. Any contamination, particles, or the presence of native oxide on the Si surface can become a nucleation site for crystallographic defects (Figure 2),45 such as a stacking fault, a microtwin, a dislocation, or their combination during epitaxial growth. Strain engineering process control and epitaxy, in general, have benefitted multifold46,47 with the advent of in situ chemical cleaning based on the chemical oxide removal (COR) process (commercially known as the Siconi process) which eliminates queue time constraints for wet (HF) chemical cleaning prior to epitaxial growth of Si or Si based materials. For example, it is now possible to grow defect-free epitaxial Si or SiGe layers at temperatures of lower than 550° C which was considered inconceivable for a reduced pressure chemical vapor deposition (RPCVD) tool. Such epitaxy growth originally belonged exclusively to the ultra-high vacuum chemical vapor deposition (UHVCVD) based epitaxy processes. This chemical cleaning capability has also enabled a number of additional process advancements: (i) incorporation of dopants and non-dopants in transistor’s source-drain regions at levels exceeding 1021 cm-3 (at process temperature lower than 600° C) that is well above their solid solubility limits in Si. Not only does such high doping levels allow the formation of low contact resistance contacts but it also imparts measurable tensile and compressive stress in the Si channel depending on the dopant type. (ii) incorporation of substitutional carbon (C) at >1% level in Si became possible due to epitaxy at <550° C and this allowed uniaxial tensile strain in 22 nm nFETs via embedded Si:C source – drain regions,23 (iii) enabling formation of raised source-drain in fully depleted silicon on insulator (FDSOI) technology where conventional epitaxy led to balling up of ultra-thin Si (<10 nm) during a standard >900°C H2 pre-bake to desorb the surface oxide,48 (iv) excellent control over the etch profile in shallow trench isolation (STI) because in situ surface cleaning by Siconi based process is agnostic to oxide density changes regardless of thermal or deposited oxide. The undesirable oxide foot on the fin sidewall that creates open voids in the oxide fill material during conventional wet etch process can now be eliminated.46
Historically, an elevated level of moisture is present right after epi chamber clean with tens of liters of HCl flow per minute for an extended period. Any residual moisture left in the epitaxy chamber can form SiO2 on Si resulting in defective epitaxial growth. However, latest advances in gas purifier technology with moisture control at parts per billion level in conjunction with the Siconi process has allowed defect-free epitaxial Si growth even at temperatures of <600°C.
B. Interface trap density (Dit) challenge in strained SiGe FinFETs
One of the major reasons that silicon has been elected as a standard material for semiconductor industry is the quality of SiO2 and Si interface. Interface quality control is always be the challenge when looking into other channel materials. Replacing conventional Si channel material by SiGe increases interface trap density (Dit), which adversely affects both hole mobility and subthreshold leakage of pFET. The Dit value in SiGe pFETs is higher due to two main reasons: (i) channel surface orientation: the dominant surface orientation in FinFET occurs on  fin sidewall compared to  surface orientation in planar FETs,49,50 and (ii) an interfacial oxide contains a mixture of SiO2 and GeOx components (rather than pure SiO2) which increases Dit.51,52 The increase in Dit on the fin structure is 1.4x higher compared to the planar (100) structure.34 A systematic set of data showing the effect of Ge content in SiGe on Dit, is shown in Figure 3. Note that all the processes, such as epitaxial growth temperature of SiGe, deposition of an interfacial layer (IL) and high-k dielectrics, and device fabrication process remained identical in this study. There is a monotonic increase in Dit with increasing Ge content in SiGe fins.
Several approaches including varying IL formation, optimizing high-k and metal gate stack, varying thermal budget in replacement metal gate (RMG) process module, adjusting H2 anneal temperature, passivation by epitaxially grown thin Si cap (<1nm), and even lowering Ge content have been attempted to reduce Dit. Amongst all the trials, Si cap reduced Dit the most effectively.41 However, there are a number of factors that need to be considered for passivating the SiGe fin using this approach: i) the Si cap must be on the order of a monolayer to reduce any capacitive penalty in an already aggressively scaled gate stack, ii) the SiGe sidewall has  crystalline surface which makes uniform (smooth) growth more challenging, and iii) the Si monolayer must be continuous, or pinhole-free, to properly passivate the SiGe interface. It was observed that the Si layer is discontinuous (Figure 4a), though low-temperature silane-based Si growth permits smooth and controllable growth down to the monolayer thickness scale. This was shown by exposing a silane-grown ultra-thin Si capped SiGe film to an etchant53 that selectively etches SiGe and not Si. Subsequent SEM imaging shows localized regions where the etchant attacks SiGe whereas other regions are remained intact. In contrast, a dichlorosilane (DCS)-based growth process showed pinhole-free growth for Si films in the same monolayer thickness regime (Figure 4b). These data suggest that continuous Si monolayers provides a possible pathway for SiGe fin interface passivation. Figure 4c (high resolution TEM) shows a DCS/HCl based Si cap of 2 monolayer thickness. Such Si caps on strained SiGe pFinFETs have indeed reduced Dit by a factor of 0.2x.41
III. STRAIN ENGINEERING FOR FUTURE Si BASED CMOS TECHNOLOGY
Current CMOS device architecture is based on FinFETs since 22nm node and the key scaling parameter is gate pitch (or known as contact poly pitch: CPP) to enable transistor density increase per CMOS generation. Aggressive CPP scaling (<60nm) has led to extremely small channel area in the current 7nm technology node which poses a serious challenge to strain engineering. This trend will continue to future CMOS generations with even greater challenges. Details of device scaling can be found in Ref. 54. In this section, we discuss strain engineering in such a tight gate pitch regime via a strained SiGe channel as well as process induced strain. Strain engineering in future device architecture such as gate-all-around nanosheet is also discussed.
A. Strained SiGe FinFETs: Device integration and characteristics
A typical process flow to fabricate CMOS FinFETs with a strained SiGe channel is shown in Figure 5a. It should be realized that the act of patterning a pseudomorphically grown SiGe epitaxial layer into fin structures naturally results in the desired outcome in that nearly complete elastic relaxation of strain occurs in the short dimension, and preservation of strain in the long direction of the fin. In practice, however, the combination of SiGe film thickness and strain (or, equivalently, Ge content) required for a meaningful improvement in hole transport renders the initial (blanket) film growth energetically unstable against the formation of strain-relieving dislocations. The challenge then becomes how to suppress defect nucleation and growth in the SiGe films until the fin structures are patterned. An alternative approach could be to selectively grow the SiGe fins in lithographically defined openings in a dielectric mask. However, this approach has high propensity of creating stacking faults along dielectric/crystalline growth interfaces. Generally, the fin structures are formed by dry etching which results in rough sidewalls. Complicating things further is the known difficulty in electrically passivating SiGe surfaces compared to pure Si, which is discussed in a previous section (Section II B).
The preservation of strain in supercritical SiGe epitaxial films can indeed be accomplished within a wide range of thickness values providing relatively low (less than 1%) misfit strain. In this strain regime, dislocations are typically generated from imperfections at the growth interface or the wafer edge. Earlier works55,56 on SiGe film metastability did not consider the role of interfacial contaminants when establishing processing constraints on film relaxation. More recent work57 demonstrated that interfacial oxygen (and the subsequent formation of stacking fault tetrahedra) plays a dominant, if not exclusive, role in the stability of supercritical SiGe films. It was shown that by reducing the amount of oxygen at the SiGe/Si growth interface to a value below ∼1012atoms/cm2, no dislocations could be formed in a 100nm thick Si0.79Ge0.21 film even after 1000°C annealing. Continuous improvements in gas purification and crystal growth equipment (as described above) have made this extremely low level of interfacial contamination achievable with proper surface preparation. The above described learning has been the backbone for designing growth parameters and Ge content to create defect-free strained SiGe in patterned recessed Si regions designated for pFETs (Figure 5b). The Ge content is kept below 20% (or 0.75% strain) for the reasons described above. Further process and integration details are described in references 39 and 41.
A comparative device study was performed in strained SiGe pFETs with and without the DCS based Si cap and the results were benchmarked against Si pFETs.41 Note that DCS based Si cap is the key enabler to achieve good interface quality for strained SiGe technology as described in the previous section. Figure 6 shows cross section TEM images of SiGe pFinFETs with and without a DCS based Si cap. The benefit of Si cap process is shown in Figure 7a, where near-ideal linear subthreshold slope of 62mV/dec is achieved at gate length of 100nm. Moreover, short channel pFET DC performance76 is improved by 15% by DCS based Si cap process as shown in Figure 7b. Figure 8 compares long channel hole mobility between the strained SiGe and Si pFET where 60% mobility improvement is observed with strained SiGe pFinFET. We believe the strained SiGe based pFET technology has a high potential of making inroads at the future CMOS technology node such as 5nm node and beyond, where strained SiGe will provide higher strain/higher performance than its counterpart strained Si channel by embedded S/D SiGe.
B. Strain engineering in gate-all-around Si nanosheet technology
As scaling of conventional FinFET architecture becomes more complex and achieving target transistor density and performance becomes harder, it is essential to seek for next generation transistor architecture. Gate-all-around structure58–60 has been explored for better electrostatics compared to conventional FinFET, however lack of current drivability due to small effective channel width remained as a major concern.59 This has been overcome by stacking the channel, which is horizontally stacked gate-all-around (GAA) nanosheet (NS) or nanowire.61,62 Stacked NS structure (Figure 9a) inherently results in a larger fin perimeter in a given designed foot print compared to conventional FinFET, which allows for a more versatile device design. Stacked NS benefits circuit performance compared to scaled FinFETs due to its nature of having larger fin perimeter in a given foot print along with superior electrostatics enabled by gate-all-around structure (Figure 9b). There are options to engineer channel strain in NS devices. A starting NS structure, containing pseudomorphic Si 0.65Ge 0.35 sheets, begins with inherent compressive strain of 1.5% lattice deformation in SiGe layer (Figure 10). After patterning and etching steps defining the sheet width, the SiGe sheets in the structure is partially relaxed63 (Figure 11), inducing a significant tensile strain in silicon sheets. An additional relaxation of the strain in active silicon layer is expected at later two steps, 1. During embedded S/D formation where the stack in S/D region is recessed, and 2. During active channel release operation where SiGe layer is removed selectively.64 Even though embedded SiGe is grown in recessed S/D regions, its effectiveness to produce strain diminishes for two reasons: (i) tight CPP with a limited SiGe volume, and (ii) relaxation of embedded SiGe by a high density of stacking faults (SFs) due to the presence of inner spacers dielectrics (Figure 12).
C. Process induced strain engineering in interlayer dielectric (ILD) films
Process induced strained film is another way to introduce strain in a transistor channel. Contact etch stop layer (CESL) (or so-called silicon nitride (SiN) stress liner) has been widely used in the old planar technologies from 90nm to 32nm technology nodes.20,24–26 The effectiveness of strain transfer from CESL to an active channel has been weakened and diminished as transistor scaling advanced for two reasons, 1. CESL thinning, 2. Implementation of 3D structure (i.e. FinFET), which makes stress transfer less effective compared to planar structure.65 Common approach to introduce strain in more advanced technology, such as 14nm, 10nm, and 7nm node CMOS FinFET, is via tensile or compressive interlayer dielectric (ILD) deposition around source-drain and metal gates.66–68 The ILD approach appears to be re-incarnation of CESL approach. Typical strain levels of higher than 0.5% silicon lattice deformation are achievable by the ILD approach in FinFET technologies (Figure 13). The level of strain depends on an amount of a stressor and a distance from a stressor to a channel, hence a degree of strain depends on layout. An inverter drive strength enhancement has been reported by designing gate cut layer preferable for both n/pFET.66 The levels of strain achieved by the technique are expected to be lowered as technology advances due to a lesser volume of ILD. Also, the effect depends on transistor architecture as well as channel material properties, and it is essential to re-evaluate the effect with the future technology with different transistor architecture and/or channel materials.
IV. STRAIN ENGINEERING IN NON-Si MATERIALS
A. Strain engineering in gallium nitride (GaN)
As strain engineered devices have become mandatory in Si-based high-performance CMOS technology, other semiconductor materials, such as GaN, are also using the strain manipulation concept to improve device performance. Gallium nitride is an important semiconductor material for both its high-power/high-frequency characteristics as well as its optoelectronic properties.69 Because optical emission from a semiconductor diode (LED) has a wavelength that is determined by the bandgap of the material, it is very difficult to have a single semiconductor material produces red, green and blue light for display applications. Having a single semiconductor material provide all three colors would be highly desirable as the only other method would be to heterogeneously integrate different materials onto a carrier substrate. Recently, it was shown70 that by growing a highly strained InGaN multi-quantum well (MQW) LED structure on GaN, and patterning the LEDs into nanoscale pillars of various radii (Figure 14), optical emission covering the range from blue to red could be achieved. The emission from blanket (fully strained) GaN regions was red (∼650nm) and as the fabricated pillar device radii was reduced from largest (800nm) to smallest (40nm) the emission wavelength decreased from amber (∼630nm) to blue (∼470nm), respectively. The elastic strain relaxation of the pillars was successfully modeled using a 1D analytical model which enabled good predictability of emission wavelength for a given pillar diameter. The use of nanoscale strain engineering to potentially enable monolithic integration of RGB micro-LEDs71 could have a large impact on micro-display technology. Another application of strain engineering in GaN-based LED technology is recent work72 suggesting that the application of biaxial strain to thin film GaN LEDs, using an electrodeposited Ni layer, increased the optical efficiency. The origin of this improvement was claimed to be due to the reduction of compressive strain in the InGaN MQW structure which naturally arises due to the lattice mismatch as well as the thermal mismatch of the underlying sapphire substrate.
B. Strain engineering in 2D materials
Ever since the discovery of graphene, the field of 2D material has exploded with a variety of new transition metal dichalcogenides (TMD) such as MoS2, MoSe2, WS2 and WSe2 with varying band gaps and physical properties. These materials are produced predominantly by three methods, namely, mechanical exfoliation, liquid phase exfoliation, and gas phase epitaxy. There are a number of ways in which strain has been applied to 2D materials because of their extreme mechanical flexibility. These include applying (i) uniaxial, (ii) bi-axial, (iii) cantilever bending, or (iv) extra-neutral strain, (v) piezoelectric stretching, and (vi) controlled wrinkling. These materials exhibit strong in-plane covalent bonds and weak van der Waals out-of-plane forces. The conductivity of these 2D materials can range from that of an insulator to all the way to that of a superconductor as shown schematically in Figure 15. One of the fascinating properties of the new families of two-dimensional crystals is their high stretchability (>10% elastic strain) and the possibility to use external strain to controllably manipulate their optical and electronic properties.73 Furthermore, reversible structural phase transition in these materials from semiconducting phase to metallic phase as a function of strain provides an interesting possibility to fabricate sophisticated flexoelectric devices, novel switches and perhaps provide the ultimately scaled CMOS transistors.
The outstanding stretchability and associated band structure changes are likely to revolutionize the field of strain engineering. Availability of this unprecedented strain tunability range should allow a new class of optical, electrical, and mechanical devices. The modulation of electronic band structure also affects the phonon modes and lattice vibrations as well as magnetic properties which may have applications for quantum computing. We now summarize 2D strain engineering of two material systems which have been studied the most to date.
1. Strain engineering in graphene
Even though graphene is the first 2D material which have unique mechanical and electrical properties, lack of a band gap has prevented its widespread usage in microelectronics and other fields. For this reason, application of strain to open the graphene band gap has been the subject of extensive research. Initial theoretical work indicated that > 10% uniaxial strain may allow band gap opening which created excitement in the scientific community. However, latest tight-binding and density functional theory calculations have ruled out this possibility for a single layer structure. Apparently, the strained Brillouin zone, which showed a “gap” at the K points initially had no real band-gap at the Dirac points and the K points and the Dirac points did not coincide. Nevertheless, other engineering options are being studied to induce permanent uniaxial strain in graphene with some success. For example, both uniaxially strained bilayer of graphene with inhomogeneities,74 and anchored graphene in patterned structures have demonstrated band gap opening. Uniaxially strained graphene with band opening has applications in the field of quantum confinement of carriers, and generation of pseudomagnetic gauge fields exceeding 10T.74
2. Transition metal dichalcogenides
Unlike graphene, uniaxial strain can be easily applied on atomically thin 2D single-layers of TMDs and these strained materials are being extensively studied for a variety of applications including microelectronics, strain gauges, and quantum dots. For example, MoS2 which has a direct bandgap of 1.8eV and an in-plane mobility of up to 200 cm2V-1s-1 has been used to fabricate FETs that have shown an impressive Ion/Ioff ratio of >107 in conjunction with ultralow standby power dissipation. Single-layer MoS2 has a remarkable property in that it can undergo a direct-to-indirect bandgap transition at ∼ 2% of tensile uniaxial strain, and a semiconducting-to-metal transition at 10-15% of tensile biaxial strain. MoS2 application is also being explored for photovoltaics applications using its exciton funneling property. Apparently, wrinkles that create strained 2D MoS2 induce funneling of photogenerated excitons from flat regions to the wrinkled regions.75 The wrinkles serve as traps with a local confinement potential for excitons.
V. FINAL REMARKS
In this review, we discussed strain engineering of Si-based CMOS transistors from planar technology to the most advanced 3D CMOS architecture known as FinFET. It is clear that strain in Si channel via embedded SiGe source - drain will diminish as a transistor gate pitch (or contacted poly pitch: CPP) continues to shrink with each passing CMOS technology node. Key drivers for strain engineering in current FinFETs will be: (i) strained SiGe pFinFET with channel interface engineering, and (ii) ILD stressors with local layout effect (LLE) engineering. Whereas strain scaling of Si channels is at the end of its tether, strain engineering in a future CMOS architecture such as gate-all-around stacked nanosheet is still at its evolutionary stage and has the potential to enable performance boost for future CMOS technology node. Potential benefits of strain engineering in non-silicon materials such as 2D materials are quite extraordinary. However, it remains to be seen if and when a true breakthrough application with these materials will happen.
The authors would like to acknowledge contributions of Albany and Yorktown research teams whose published work is the basis of this review. We gratefully acknowledge early work of Lisa Edge on the Si cap for Dit reduction in SiGe channels.