High k dielectrics, such as Al2O3, has attracted increasing research attention for its use as the gate dielectric of 4H-SiC MOS capacitors. Since the dielectric constant of Al2O3 is not high enough, many other high-k dielectrics are actively explored. In this letter, a report of the interface properties of 4H-SiC MOS capacitors with Hafnium silicate (HfSiOx) dielectric is presented. The HfSiOx dielectric was deposited by thermal atomic layer deposition. A systematic study of I-V and multi-frequency C-V characteristics were carried out and the results showed HfSiOx gate dielectric could effectively increase dielectric constant. A thin layer of SiO2 in between SiC and high k dielectric can further improve interface properties. These results indicate that HfSiOx could be a promising candidate as suitable gate dielectric material for future 4H-SiC MOS capacitors and MOSFETs.
Silicon carbide (SiC) is a wide bandgap semiconductor which holds great promise for next-generation power devices. Due to its wide bandgap, high breakdown field strength and high thermal conductivity properties, 4H-SiC has a great advantage compared with conventional silicon on power electronics targeting high power, high temperature and high working frequency applications.1 However, there is a severe problem with the dielectric stability at high electric field. Since the dielectric constant of SiC is much higher than that of SiO2, the electric field in SiO2 is always much higher than that of SiC, especially when it reaches the critical field of SiC at 3 MV/cm, which will lead to a severe reliability problem for the SiO2 dielectrics.2 High k dielectrics can be applied on SiC to alleviate the electric field in the gate dielectric1 and some example high k materials are Al2O3,3,4 HfO2,5–7 AlON8 and La2O3.9,10 A study with Al2O3 as the gate dielectrics was taken and it showed using Al2O3 could increase the dielectric constant, thus improving the stabilities of the gate dielectric of SiC MOS capacitors.11 Gate dielectric with even higher dielectric constant such as Hf-based HfSiOx is expected to improve the performance further.
In this letter, all the MOS capacitors were fabricated by using a commercial n-type 4H-SiC (0001) substrate (4° off-axis) with an n-type doping level of 8×1015 cm-3. Each sample was cleaned by a standard RCA cleaning process, followed by a dip of 60s in diluted BOE to remove the native oxide. After the cleaning, 20nm HfSiOx was deposited by atomic layer deposition (ALD). HfSiOx dielectric was deposited at 300 °C with Tetrakis (dimethylamino) hafnium, Tris (dimethylamino) silane and ozone as precursors. The XPS and X-ray powder diffraction (XRD) data of the film are shown in Figure 1. The molar concentration of SiO2 within the HfO2 host lattice is ∼ 4 %. Then these samples were thermally annealed in oxygen atmosphere at various temperatures for 30 minutes. After that, 20 nm Ni and 50 nm Au layers were deposited by e-beam evaporation as contact pads as shown in Figure 2. Finally, electrical measurement of C-V and I-V characteristics of these devices was carried out by using the Agilent B1505.
As can be seen from Figure 3, it could be found that the annealing temperature affects not only the flatband voltage shift, but also the threshold voltage. It is clear to see the 900°C to 950°C is the optimized temperature range for annealing from the flatband voltage shift. The k can be calculated by the equation
where C is the gate oxide capacitance of C-V curves measured at 1 MHz, tox is the thickness of gate dielectric (20 nm), and S is the area of MOS capacitor. As shown in Figure 4(a), the dielectric constant changes with different annealing temperature, and reaches the peak values at around 850°C. Figure 4(b) shows the flatband voltage shift at different annealing temperatures. It could be clearly found that the devices annealed at temperature from 900°C to 950°C in oxidation atmosphere have the lowest flatband voltage shift. High temperature annealing can significantly reduce the negative charges located at near interfaces and in the oxides. Therefore, the flatband voltage decreases from 800 to 950 °C. The higher temperature could cause the formation of SiOx interfacial layer, resulting in the increase in the flatband voltage.
(a) k, (b) ΔVfb, and (c) Frequency dispersion of SiC MOS capacitors with HfSiOx dielectric annealed at different temperature.
(a) k, (b) ΔVfb, and (c) Frequency dispersion of SiC MOS capacitors with HfSiOx dielectric annealed at different temperature.
The effective trapped charge density Nit is defined by the equation12
where Cox is the gate dielectric capacitance per unit area. The devices annealed at 925°C exhibit a very low trapped charge density of 42.6×1010cm-2. Figure 4(c) shows the frequency dispersion Hfd reduced drastically from 850 °C and above, also indicating a low density of interface trap.
Taking into all the factors including k, ΔVfb, Nit and frequency dispersion, the overall optimized performance can be obtained at around 925°C annealing temperature for the HfSiOx/4H-SiC MOS capacitors. All the results were shown in Table I.
The properties of SiC MOS capacitors with HfSiOx dielectric annealed.
| Dielectric material | k | ΔVfb (V) | Hfd (%) |
|---|---|---|---|
| HfSiOx | 12.8 | 0.12 | 3.87 |
| Dielectric material | k | ΔVfb (V) | Hfd (%) |
|---|---|---|---|
| HfSiOx | 12.8 | 0.12 | 3.87 |
However, it is noted that there is still room for further improvement in frequency dispersion. Previous studies show that a thin layer of SiO2 deposited between 4H-SiC and high k dielectric can improve the interface quality, compensate the low band offset and block the electron injection into SiC layer, decreasing the leakage current and interface trap density.13,14 Therefore, some supplemental experiments were carried out.
After cleaning the 4H-SiC epi wafers, a thin SiO2 layer with the thickness of 5 nm was grown at 1050°C in thermal dry oxidation atmosphere. Then 20 nm HfSiOx layer was deposited on SiO2 layer at 300°C by ALD. After that, the samples with HfSiOx/SiO2 dielectrics were annealed in dry oxidation atmosphere. Finally, 20 nm Ni and 50 nm Au layer were deposited on these caps.
Figure 5(a) shows the frequency dispersion of SiC MOS capacitors with HfSiOx/SiO2 dielectric annealed at different temperature. Again, the annealing temperature of 925°C shows the best performance. It acquires the lowest frequency dispersion and the best uniformity. The calculated result of frequency dispersion is 1.58%, which is lower than half of the value for the sample without SiO2 layer, as shown in Table I. Figure 5(b) shows the C-V curves of the SiC MOS capacitors with HfSiOx/SiO2 dielectric annealed at 925 °C. As expected, the calculated result of k of this composition layer is around 10, lower than the value with HfSiOx single layer. The I-V characteristics were also tested for comparison, as shown in Figure 6(a). It can be seen that the gate leakage current density is much lower with the thin layer of SiO2 in between. The curve of current density vs electric field (J-E) was also plotted in Figure 6(b). A transmission electron microscope (TEM) image is taken in Figure 7 to show the interface of the HfSiOx/SiO2/SiC structure.
(a) Frequency dispersion of SiC MOS capacitors with HfSiOx/SiO2 dielectric annealed at different temperature. (b) C-V curves of the SiC MOS capacitors with HfSiOx/SiO2 dielectric annealed at 925 °C.
(a) Frequency dispersion of SiC MOS capacitors with HfSiOx/SiO2 dielectric annealed at different temperature. (b) C-V curves of the SiC MOS capacitors with HfSiOx/SiO2 dielectric annealed at 925 °C.
Gate leakage properties of the SiC MOS with HfSiOx VS HfSiOx/SiO2 gate dielectric annealed at 925 °C. (a) I-V, (b) J-E.
Gate leakage properties of the SiC MOS with HfSiOx VS HfSiOx/SiO2 gate dielectric annealed at 925 °C. (a) I-V, (b) J-E.
In summary, we have reported the interface properties of SiC MOS with HfSiOx gate dielectric. The high k material HfSiOx has enhanced the gate dielectric constant dramatically, and therefore lower electric field could be acquired in the dielectric layer and higher long-term reliability for the SiC MOSFET could be expected. In order to improve the interface quality in further, a thin layer of SiO2 with about several nanometers is proved to be necessary by experiment.
This work was supported by State Key Laboratory of Advanced Electromagnetic Engineering and Technology (Huazhong University of Science and Technology) (2016KF004) and the Key Basic Research Program of Hubei Province under Grant 2017AAA127.
