Fully tensile strained partial silicon-on-insulator n-type lateral-double-diffused metal-oxide-semiconductor field effect transistor using localized contact etching stop layers Open Access

Silicon-on-insulator lateral double-diffused metal-oxide-semiconductors (SOI LDMOSs) can be used as cost-effective and reliable power transistors with good linearity; they have received particular interest for use in radio frequency power amplifiers, a critical component of all wireless system-on-a-chip applications.^1–3 Isolated by a buried box layer, SOI LDMOS field effect transistors (FETs) have benefits such as a reduced leakage current, reduced parasitic capacitance, and reduced cross-talk via the substrate. However, LDMOS devices based on SOI technology have some disadvantages, such as their self-heating effect (SHE) and kink effect.^4–6 Partial SOI (PSOI) LDMOSFETs are devices that have emerged that can spread heat into the substrate through a Si window and eliminate floating body effects.^7,8 However, owing to the rapid development of semiconductor processes, the top Si thickness of the SOI wafer has been reduced to less than 20 nm to achieve full depletion to decrease the parasitic capacitance. As a result, LDMOSFETs based on SOI will suffer from reductions in their frequency and power efficiency owing to drift resistance increases when integrated with CMOS circuits.

In this paper, we propose a thin film n-type PSOI LDMOS with a low drift resistance, high cut-off frequency, and desirable breakdown characteristics by introducing tensile stress into both the channel and drift region via contact etching stop layers (CESLs). The uniaxial tension in the channel and drift regions splits the degeneracy in both the conduction and valence bands and reduces the bandgap,⁹ which decreases the in-plane effective mass and reduces inter-valley scattering;¹⁰ thus, the proposed device’s electron mobility is increased. Simulation results show that the proposed PSOI LDMOS device has a better frequency performance and driving capability than an unstrained PSOI LDMOS device has over a wide range of gate biases.

Fig. 1 shows the proposed device structure, where intrinsic tensile and compressive stress CESL layers have been applied in regions A and B, respectively. The device also includes an optimized polysilicon field plate that partially overlaps the drift region and is connected to the gate to further adjust the drift region stress.

To investigate the effect of using a CESL stressor structure on reducing the drift resistance and improving the cut-off frequency, Sprocess and Sdevice modules of Sentaurus TCAD tools were used to generate and evaluate the LDSMOS structure shown in Fig. 1. The thickness of the top Si layer (T_SOI), the length of the BOX layer (L_BOX), the thickness of the BOX layer (T_BOX), the thickness of the gate oxide (Tox), the thickness of the field plate oxide (Tp), the thickness of the drift region (t_d), the length of the Si window (L_Si), and the width of the field plate (Lp) are defined, as shown in Fig. 1, and their initial values are listed in Table I. To conveniently discuss the detailed effects of fully straining the structure on its stress distribution and electrical properties, the above mentioned optimized parameters are considered in the following regions. Two types of PSOI LDMOS transistors were simulated as control samples with the same parameters of the proposed PSOI LDMOSFETs (except for the CESL layer), i.e., devices with a CESL layer in region A and B with no intrinsic stress (normal unstrained), and devices in which the CESL layer was intrinsically stressed (tensile) with 2 Gpa For fully strained devices, a 150 nm CESL layer with a 1.6 Gpa intrinsic compressive stress on the drift region (B), and a 2 Gpa intrinsic tensile stress on the other regions (A) are defined.

For the simulations, the thermodynamic and hydrodynamic transport model, the density gradient quantization model, the Fermi statistics, the Philips unified mobility model, doping-dependent mobility model, mobility degradation at interface model, high field saturation model, the SRH recombination model, the Auger recombination model, the deformation potential model, the stress-induced electron mobility model, the intel-stress-induced hole-mobility model, the effective mass of an electron and hole model, and the avalanche breakdown model were used.

Fig. 2 shows the stress contour lines of the strained channel and of the fully strained PSOI LDMOSFET for T_SOI = 50nm. Unfortunately, owing to the presence of the gate structure, the continuous CESL layer was interrupted and thus has two edges on both sides of the channel so that the silicon exerts stress on the silicon beneath it. When the tensile stress exists in the channel for the channel strained device, the silicon crystal lattice is stretched by regions outside of the channel’s two edges. Owing to the continuity of the crystal lattice, the proximate drift region was compressed, i.e., a compressive stress (Fig. 2a). This phenomenon, namely that the CESL localization has an unfavorable effect on the electron mobility, also causes the on-resistance (R_on) to degrade. To reduce R_on effectively, the CESL layer in the drift region (region B in Fig. 1) was changed from a tensile to a compressive and then to stretch the drift region. As shown in Fig. 2(b), the stresses both in the channel and drift region of the proposed device are effectively tensile stresses.

Fig. 3 compares the stress distribution and carrier mobility along the channel direction at a depth of 2 nm below the Si surface for the normal PSOI LDMOSFET, the classic channel strained device, and the proposed fully strained device. It is obvious that, in drift region, the stress of the fully strained LDMOS device changes from compressive to highly tensile compared with the channel strained device; this leads to a carrier mobility enhancement of over 35.3% compared with the normal unstrained device, while the carrier mobility of the channel strained device is reduced by about 26.27% compared with a normal device without stress.

Considering the size and location of the BOX layer, the length of the gate field plate might affect the stress distribution; the average stress in the drift region of the two types of strained LDMOSFETs are therefore shown in Fig. 4. In the simulation, the BOX length L_BOX is varied from 0 to 400 nm, the BOX thickness T_BOX from 0 to 400 nm, the top Si thickness T_SOI from 20 to 300 nm, and the gate field plate length from 10 to 60 nm. It can be seen that the BOX dimensions do not have much effect on the average stress in the drift region (less than 200 MPa for the fully strained device and less than 10 MPa for the channel strained device), which does not change the carrier mobility nor the device’s electric characteristics significantly. Meanwhile, the gate plate length has a greater impact on CESL stress localization than the BOX layer for the channel strained device. As the length of the field plate was increased, the average stress in the drift region of the channel strained LDMOSFET quickly changed from compressive to tensile, while the stress of the fully strained LDMOS device remained relatively unchanged.

Owing to the fact that drift region resistance predominates the on-state resistance for LDMOS, the frequency performance of the proposed device was improved effectively, as shown in Fig. 5. It can be seen that the cut-off frequency (f_T) of the two strained devices achieved an enhancement of over 25.5% compared with the unstrained normal LDMOSFET at a low gate bias (V_g < 0.7 V). But the enhancement magnitude of channel strained device decreased as V_g was increased and was even lower than that of the normal unstrained device for V_g > 1.5 V. Nevertheless, the fully strained device still shows a significant increase in f_T compared with the channel strained device and the unstrained normal device at high V_g. Usually LDMOS transistors used in radio frequency power amplifiers operate in switching-mode, which means that V_g is often much higher than the threshold voltage V_th (0.47 V, 0.51 V, and 0.53 V for channel strained, fully strained, and unstrained devices, respectively). As a result, the enhancement of f_T over a wide range of V_g will play an important role in increasing circuit speeds.

The inset in Fig. 5 shows the on-resistance and breakdown voltage of the three types of LDMOSFETs with T_SOI varying from 20 to 230 nm. Obviously, T_SOI has a strong negative effect both on R_on and BV, especially when T_SOI is reduced to below 100 nm. The effect of a normal CESL stressor (channel strained) on R_on is gradually weakened and is even counterproductive for T_SOI layers thinner than 50 nm. The R_on of the proposed fully strained device is maintained at a low value over a wide range of T_SOI. Meanwhile, stress does not alter the breakdown voltage too much either in fully strained device or in the channel strained devices because the value of the stress-induced bandgap narrowing is rather small.¹¹ 

In summary, an extremely thin film partial SOI LDMOS is proposed in this paper. Using a simulation, we showed that the channel and drift region of the fully strained LDMOS have a larger carrier mobility and that its cut-off frequency is increased by at least 25% compared with that of a conventional thin-film SOI LDMOS at Vg = 1.5 V. Furthermore, the proposed strain method is effective for step-gate LDMOSFETs, especially for small-size, extremely-thin SOI LDMOS devices.

This work was supported by the National Natural Science Foundation of China (61574027 and 61574028), the Open Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices (KFJJ201511), and the Scientific Research Project of the Land and Resources Department of Sichuan Province (KJ-2016-16).