On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

Traditionally, the MEMS and NEMS have mainly been fabricated on silicon substrate. But the poor mechanical properties of silicon severely limit the development of Si-based MEMS and NEMS applications.^1–3 The ultrananocrystalline diamond (UNCD), with its exceptional properties such as extreme hardness and a high Young’s modulus,⁴ chemical inertness and biocompatibility,^5,6 and negligible force of adhesion,^7,8 has been studied and considered as a candidate material for MEMS and NEMS devices.^9,10 The MEMS and NEMS devices based on UNCD deposited on CMOS chip can be allowed to work efficiently in critical environments.¹¹ However, a complete depiction of the changes in the electrical characteristics of CMOS after the UNCD deposition on CMOS chips have not been evaluated fully. Here we report the changes of both direct current (DC) and radio frequency (RF) characteristics of CMOS with UNCD coating. The study will provide useful guidance on the future development of monolithically integrated CMOS-driven diamond based MEMS/NEMS systems.

In this work, large-area, high quality UNCD films were grown by microwave plasma chemical vapor deposition (MPCVD). Transmission electron microscopy (TEM) - electron energy loss spectroscopy (EELS) studies were carried out for the UNCD-deposited CMOS chips in order to reveal the deposition impact on the device structure and material in CMOS. The DC and RF performance of the individual NMOS and PMOS devices were measured before and after the UNCD growth process. Systematic comparisons of these performances were carried out to evaluate the influence of UNCD growth on the Si CMOS devices. The results proved that the UNCD deposition and subsequent processing, which is in general the same as that used for processing MEMS/NEMS, did not severely degrade the CMOS devices and the functionality of the CMOS was well-maintained.

The UNCD films were deposited in a 915 MHz, 10 kW microwave plasma chemical vapor deposition (MPCVD) system at 400 °C, on 200 mm diameter Si CMOS wafers. The UNCD deposition temperature (400 °C) is within the CMOS thermal budget limit.^12,13 The microwave coupling system was designed to provide efficient energy transfer for a wide process range.¹⁴ The plasma was confined in a transparent quartz bell jar, which allowed optical detection to access and reduce the film contamination of quartz wall etching. The substrate was designed to have a two-zone (inner and outer) resistive heater to compensate for heating due to the shape of the plasma.¹⁴ The Si CMOS chips featuring 90 nm gate length were produced by commercial silicon foundries.

Prior to the UNCD film deposition, a 1 μm SiO₂ isolation layer was deposited by plasma enhanced chemical vapor deposition (PECVD) on the CMOS wafer, followed by a 10 nm tungsten (W) seed layer by sputtering. The tungsten layer was seeded using nanodiamond suspension and then subjected to the UNCD deposition process.¹⁵ At lower temperatures, the growth is sluggish due to slow surface diffusion, which can affect the initialization stability of diamond nucleation on a non-diamond substrate and make the uniformity of the UNCD film rely more on the seed profile. Because the carbon diffuses quite slowly in tungsten, the tungsten interlayer forms carbide at very early stages of diamond growth to reduce the initial incubation time for diamond nucleation.¹⁶ Thus, uniform UNCD films can be obtained on many substrates with a surface roughness close to the grain size.¹⁴ The optical image of a finished CMOS wafer with the UNCD film on top is shown in Fig. 1(a).

After finishing the UNCD film deposition, a thin Al layer was evaporated on the top surface as a hard mask layer for the via-opening process. The via-opening step for testing pads in a CMOS device was completed by the following fabrication processes. First, the UNCD layer was etched by oxygen plasma of RIE using the previous Al layer as the mask. The following tungsten layer was opened by wet etching. Finally, the PECVD SiO₂ layer was etched by the CF₄/CHF₃ plasma of RIE. The schematic and focused ion beam (FIB) cross-sections of the CMOS wafer coated with UNCD and with the CMOS test pad opening are shown in Fig. 1(b) and 1(c). Fig. 1(d) shows a top-view optical image of the finished device with UNCD before pad opening. The scanning electron microscope (SEM) images of CMOS test pads after UNCD deposition without pad opening are shown in Fig. 1(e). Fig. 1(f) shows the test pads for signal after the pad opening and clearly shows that the access to the testing pads has been completely opened.

The UNCD deposited CMOS chip samples were checked by TEM-EELS characterizations to study the UNCD quality and the impact of the UNCD growth process on CMOS. Fig. 2(a) shows the TEM cross-sectional image of the interfaces of the PECVD SiO₂ film with the tungsten seed layer and the UNCD layer on top of the CMOS wafer. The EELS spectrum shown in Fig. 2(b) proves that the UNCD is a pure phase diamond film attributed to a nucleation enhancement from the tungsten seed layer. The tiny peak at about 285 eV comes from disordered carbon present in terms of mixed sp³/sp² bonding at the grain boundaries and possibly damages induced by the TEM sample preparation process. The EELS spectra of oxygen (O) (Fig. 2(c)) and Si K edges (Fig. 2(d)) from the SiO₂ layer confirm that there is no carbon diffusing through the tungsten seed layer to contaminate CMOS.

The DC characteristics of the PMOS and NMOS were measured using an HP4155 semiconductor parameter analyzer at room temperature. The measured NMOS and PMOS devices were randomly chosen from different regions on the CMOS wafer. We particularly investigated the changes in threshold voltage (V_th), subthreshold voltage swing (SS), and transconductance (g_m), which are the key parameters in CMOS devices to examine the effects of the UNCD deposition process. Fig. 3(a) and 3(c) show the transfer characteristics of the PMOS and NMOS devices, respectively. For PMOS devices, the average change of the V_th and S values before and after UNCD deposition were measured as 0.26 V and 6.6 mV/dec, respectively, which are acceptable values for CMOS performance.¹³ The transconductance increased 13% which is probably attributed to the slightly better heat dissipation by the UNCD layer. For NMOS, the change of V_th, S, and g_m values remained the same with average values of 0.032 V, 24 mV/dec, and 25%, respectively. Overall, the results show that after UNCD deposition, the DC characteristics were still coherent to those before UNCD deposition. The corresponding output I− V curves are shown in Fig. 3(b) and 3(d) for PMOS and NMOS, respectively.

The RF characteristics of the individual device before and after UNCD deposition were further investigated. The devices were measured by the Agilent E8364A performance network analyzer from 45 MHz to 40 GHz. As shown in Fig. 4, values for the current gain cut-off frequency, f_T, and maximum frequency of oscillation, f_max, were extracted from the measured scattering parameters (S-parameters) to examine the effect of UNCD deposition and other processes on the RF performance of CMOS devices. For PMOS (Fig. 4(a)), the f_T and f_max values changed from 2.65 GHz and 10.35 GHz to 1.68 GHz and 9.42 GHz, respectively, by the UNCD layer deposition. For NMOS (Fig. 4(b)), the f_T and f_max values changed from 2.38 GHz and 5.37 GHz to 2.92 GHz and 6.26 GHz, respectively. From the above investigation on the influence of an individual device on the CMOS chip, it is clear to see that although there are some changes in DC and microwave/RF performances, the PMOS/NMOS devices not only remained functional, but also that the DC and RF performances are close to those of devices before UNCD deposition.

It is well known that thermal annealing can cause the degradation of the charge carrier transportation property, such as mobility, by damaging the Si crystal structure.^17,18 In this work, the UNCD deposition temperature is not sufficiently high to cause damages to the Si crystal structure. Instead, the UNCD process, which is equivalent to a post-annealing process to the finished CMOS chip, could have caused degradation of the metal contacts due to unwanted dopant out-diffusion at some degrees and also possibly metal/Si inter-diffusion in MOSFETs.^19,20 However, as shown in Fig. 4, only small changes in both DC and RF performances of the CMOS were found after the 400°C UNCD deposition process. The small degradation of the CMOS characteristics suggests that our low temperature MPCVD process for the additional UNCD layer deposited on CMOS was successfully implemented. As a result, the compatibility of UNCD process designed for the CMOS-driven MEMS/NEMS devices for monolithic integration of these the diamond-based mechanical devices with CMOS is proved to be feasible.

In summary, a low temperature (∼ 400° C), large area, high quality UNCD film was deposited by MPCVD on a finished Si CMOS wafer for monolithic integration with MEMS/NEMS applications. The DC and RF performances of an individual device (PMOS/NMOS) on the CMOS chip before and after UNCD deposition were systematically studied. A comparison of electrical characteristics confirmed that the CMOS devices with a UNCD layer keep the functionality and maintain the device performance at a similar level. This work demonstrated that low temperature UNCD deposition is compatible with conventional CMOS chips and that UNCD MEMS/NEMS can be monolithically integrated with and can directly be driven by on-chip CMOS electronics.