Trap behaviours characterization of AlGaN/GaN high electron mobility transistors by room-temperature transient capacitance measurement

AlGaN/GaN-based high electron mobility transistor (HEMT) is considered as a promising candidate for power device applications in the field of power grid, automobiles, wireless communication, and etc. As compared with conventional Si-based power devices, owing to the material property advantages of GaN (e.g. wider band gap energy of 3.45eV, lower specific on-resistance, larger critical electric field, excellent thermal stability etc.), AlGaN/GaN HEMTs can achieve higher current density, lower switching energy loss, higher breakdown field and higher frequency.^1–3 Recently GaN-on-Si substrate attracts a lot of attention due to its low cost towards mass production.^4–6 It is also noted that the high-K dielectric application in AlGaN/GaN HEMTs have also been actively studied, like the high-K application in the field of thin film transistors.^7,8 However, the reliability of AlGaN/GaN HEMTs is still of a great concern.⁹ Some researchers have associated the major degradation mechanisms in AlGaN/GaN HEMTs such as the current collapse,¹⁰ threshold voltage shift,¹¹ and the increase of the gate/drain leakage current¹² with the deep level traps in the device.¹³ On the other hand, a clear understanding between trap behaviours and device reliability is still highly desirable.^14–20 It is reported that deep-level-transient-spectroscopy (DLTS) can assist in the quantitative analysis of the deep level defects in AlGaN/GaN HEMTs, which requires a well-controlled temperature cabinet with a wide temperature scope (dozens of K to hundreds of K).^21,22 In this work, we use a room-temperature transient capacitance measurement to study the trap behaviours in AlGaN/GaN HEMTs using 6-inches GaN-on-Si substrate. A possible model on the trapping mechanism is thus proposed to explain the threshold voltage (V_th) instability in AlGaN/GaN HEMTs based on our measurement data. Furthermore, we provide a methodology for quantitative analysis on trap density variation of AlGaN/GaN HEMTs before and after step stress applied on drain electrode based on the transient gate capacitance variance measurement.

Fig. 1 (a) shows a schematic of the AlGaN/GaN HEMTs used in this work. A $3.8μm$ unintentionally doped GaN layer followed by a 22 nm Al_0.22Ga_0.78N barrier is grown on 6-inch Si substrate using metal-organic chemical vapour deposition (MOCVD) to produce the GaN-on-Si wafer. A 2-DEG can be formed at the AlGaN/GaN interface. The mobility and 2-DEG electron density are measured to be 1900 cm²/V s and 1.2×10¹³ cm² respectively. A 35 nm SiNx layer is then deposited on the GaN-on-Si wafer as the gate dielectric using low pressure chemical vapour deposition (LPCVD). The multi-fingered gate width is 8.5 mm and the gate length is $2μm$⁠. The gate-drain spacing (L_GD) is $15μm$⁠, and the gate-source spacing (L_GS) is $2μm$⁠. TiN/Ti/Al/Ti (20/20/120/20nm) stack are deposited using sputter as Ohmic contact metal layer (source/drain region) in this device. The ohmic contact is then formed by annealing in nitrogen ambient at the temperature 850 degree C for 30s by a rapid thermal annealer. Fig. 1 (b) and (c) show the output characteristics and the transfer characteristics of the pristine fabricated device. The V_th of device is measured as around -7.5 V. The maximum drain current is $∼$ 648 mA/mm at V_gs = 7 V. The breakdown voltage is up to 750V (measured at the drain current as 0.1 mA/mm).

Room temperature transient capacitance measurement is used to study the trapping behaviours in the device. Fig. 2 displays the experimental setup system. In this system, the source and drain terminals are grounded. A cycle pulse is applied to the gate, and the corresponding transient gate capacitance is measured using a Keithley 590 fast C-V analyzer. The pulse period is 30 ms, and the width is 5 ms. In the measurement, when the pulse voltage reaches the peak value, the traps in the AlGaN layer are filled with electrons from the conduction band. The gate capacitance also reaches the peak value, as shown in Fig. 3 (a). The depletion region became wider with applied reverse pulse voltage to the gate, which leads to the drop of the capacitance. With the electrons emitted from the traps, the capacitance could slowly return back to the previous value at the steady state, shown in Fig. 3 (b). Therefore, the filling and emptying traps process induces a gate capacitance changing over time. By calculating the average of capacitance variance $(ΔC)$ in three pulse periods, a $ΔC$ ∼ t curve can be extracted. With increasing the pulse peak voltage on the gate from 1 V to 7 V with a stable reverse voltage (-4V), a series of $ΔC$ ∼ t curves are measured at the room temperature. Each measurement is repeated for 3 times, the error bar scale is around 3-4%. Note that all measurements are conducted in the dark environment since light irradiation could affect the trap behaviours.

The ΔC∼t curves under various gate pulses are summarized in Fig. 4. We observed that $ΔC$ increases with V_peak at beginning and then drops down when V_peak is higher than 3 V. It is interesting to note that when V_peak is higher than 5 V, $ΔC$ is reduced dramatically and even becomes negative. The trend of $ΔC$ under different conditions can be correlated with the trap behaviours in AlGaN/GaN HEMTs. A possible model of trapping mechanism is proposed (see Fig. 5). When the pulse is relatively small (e.g. V_peak is set to 1 V only in Fig. 4), the pulse voltage can not attract enough free electrons to fill up the deep level traps in the AlGaN/GaN HEMTs, as shown in Fig.5 (a). With the pulse peak increasing, more deep level traps can be exposed. During a cycle pulse, more electrons fill the extra defects,shown in Fig.5 (b). Therefore, $ΔC$ starts to increasing with V_peak (e.g. from V_peak = 1 V to V_peak = 3 V in Fig. 4). However, the pre-existing electron traps in SiN_X layer or at SiN_X/AlGaN interface will be activated with further increasing the gate pulse voltage, as shown in Fig.5 (c). The effect becomes more remarkable after further increasing gate pulse voltage. It can be seen that $ΔC$ is reduced dramatically and even becomes negative (e.g. V_peak increases to larger than 5 V in Fig. 4).

Following the previous experiments, the device degradation induced by the gate pulse stress and the drain electrical stress are also studied. With the pulse stress applied on the gate, it can be observed in Fig 6 that the V_th of the AlGaN/GaN HEMTs is shifted to the positive direction In addition, V_th increases rapidly at the early stage of stressing, then saturates gradually after 10 min. Based on the possible model of electron traps in AlGaN/GaN HEMTs (see Fig. 5), it is believed that the shift of threshold voltage can be partially attributed to the pre-existing electron traps in SiN_X layer or at the SiN_X/AlGaN interface.

Electrical stress applied to the device could induce both temporary and permanent current collapse because of electron traps in AlGaN/GaN HEMTs.²⁴ The drain stress induced trap density changing is studied based on the above-presented transient capacitance measurement. A step-stress (see Fig.7) is applied to the drain electrode with a negative bias of -15 V on the gate (device is at off-state). The transient capacitance characteristics before and after stressing are shown in Fig.7 (b). It can be seen that the capacitance variance $(ΔC)$ increases after the drain step-stress. Based on the above-presented trapping model, the increment of capacitance variance is believed to be correlated with the increment of deep level defects concentration in AlGaN/GaN HEMTs. Since the applied stress bias on drain could cause the accumulation of the deep level traps, more electrons can fill up the traps, and thus to be emitted at the steady state. Therefore, the capacitance variance could increase after drain stress, which is similar with the increment of capacitance variance when gate pulse increases from a small value (e.g. from Vpeak = 1 V to Vpeak = 3 V in Fig. 4). To quantitatively analyse the traps behaviours, the trap density is estimated based on the Equation (1).¹⁸ 

Where C₀ is the capacitance value of steady state, N_T is the trap density and N_D is the doping concentration respectively.²³ The transient change of capacitance $ΔC$ is calculated from a time window of 15ms. Before applied step-stress, the value of $ΔC$ is 0.92×10^-11 F. After applied step-stress, $ΔC$ increases to 1.12×10^-11 F due to the step-stress induced extra traps. Doping concentration N_D can be calculated using the Equation (2):

Equation (2) indicates 1/C² is a linear function of the gate voltage V_g near the value of threshold voltage (∼ -7.7V), as shown in Fig. 8. The net doping concentration N_D ∼ 9.081×10¹⁵ cm^-3 can be determined from the relation of 1/C² and V_g. Then, according to Equation (1), Calculating the trap density before and after electrical stress are 1.404×10¹⁵ cm^-3 and 1.709×10¹⁵ cm^-3 respectively. These results match roughly with previous literatures.^25–28 Deep level traps were induced in the near-interface of SiN_X/AlGaN during electrical stress. The results are summarized in Table I.

In conclusion, the transient capacitance measurement is introduced to study the trap behaviours in AlGaN/GaN HEMTs. By the transient capacitance measurement, the trap behavior mechanism is proposed to explain threshold voltage instability of AlGaN/GaN HEMTs Furthermore, the change of traps density before and after step-stress on drain electrode is quantitatively analyzed.

This work is sponsored by the Key laboratories of third-generation semiconductor devices in Shenzhen (Grant No. ZDSYS20140509142721434), the project of 2014-084 Key Technology Development of Si based GaN power devices (Grant No. JSGG20140729145956266) and the project of Energy-efficient Si based GaN power devices (Grant No. KQCX20140522151322946), the fundamental research project of science and technology plan of Shenzhen(JCYJ20140415162542983).