Isotropic etching of bulk silicon (100) using Xenon Difluoride (XeF_{2}) gas presents a unique opportunity to undercut and release ultra-thin flexible silicon layers with pre-fabricated state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) electronics. In this work, we present design criteria and mechanism with a comprehensive mathematical model for this method. We consider various trench geometries and parametrize important metrics such as etch time, number of cycles and area efficiency in terms of the trench diameter and spacing so that optimization can be done for specific applications. From our theoretical analysis, we conclude that a honeycomb-inspired hexagonal distribution of trenches can produce the most efficient release of ultra-thin flexible silicon layers in terms of the number of etch cycles, while a rectangular distribution of circular trenches provides the most area efficient design. The theoretical results are verified by fabricating and releasing (varying sizes) flexible silicon layers. We observe uniform translation of design criteria into practice for etch distances and number of etch cycles, using reaction efficiency as a fitting parameter.

## I. INTRODUCTION

The next generation wearable and Internet of Everything (IoE) devices for applications such as advanced healthcare,^{1–3} environmental monitoring,^{4–6} robotics,^{7–9} and communications,^{10–12} require the use of broad class of electronics made from otherwise rigid and bulky silicon in a flexible and free form. These electronic circuits are required to have enough computation capability to process sensor and actuator data in real-time, while maintaining reliability over varying ambient conditions and over a long period of time. Silicon-based state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) electronics satisfy these requirements, hence, several techniques have been reported in the past to transform the rigid and brittle silicon substrate into a flexible platform.^{13,14} One of the approaches reported is known as the “trench-protect-etch-release” (TPER) method.^{15–20} In this process, the bulk silicon (100) substrate (which is used to fabricate ninety percent of the electronics) is deterministically patterned with an array of trenches and etched using deep reactive ion etching. The substrate is then subjected to conformal deposition of a “passivating” thin film to protect the side walls of the trenches from isotropic etching. The passivation layer is selectively removed from the bottom of the trenches and the substrate is subjected to an isotropic etching agent to undercut and release the top layer of the substrate. If the thickness of this released layer is small enough, the released silicon becomes flexible.^{21} This general process has been used to demonstrate flexible thin layers of various electronic substrates.^{22,23} In this work, we formulate the design criteria of this efficient CMOS compatible method for obtaining ultra-thin flexible silicon layers (fabrics).

## II. DESGIN CRITERIA

The TPER process generally entails the use of a specific reagent for the final release process which etches the substrate isotropically (i.e. independent of crystallographic planes), while being selective to the side-wall passivation layer and the top passivation layer. Further, the etch conditions should be compatible with the pre-fabricated electronic circuits in terms of chemical, mechanical and thermal considerations. In general, the reaction should form all gaseous or liquid-phase products so that the reaction does not become mass transport limited. Considering these constraints, Xenon Difluoride (XeF_{2}) is an ideal etchant for silicon substrate, since it etches the substrate isotropically, at ambient pressure and at room temperature. XeF_{2} is a light-sensitive, covalent compound which dissociates when it comes in contact with water vapor. The reaction with silicon proceeds through adsorption of the gas-phase reactant, followed by the dissociation of XeF_{2} molecule. The fluorine atoms then react with the silicon atoms to produce an adsorbed reaction product (SiF_{4}), which desorbs along with the non-reactive Xe atom to complete the reaction. The reaction produces all gas-phase products that can be pumped out of the reaction chamber to continue the reaction. The chemical reaction governing the etch process is as follows

Because the reactant XeF_{2} and the reaction products are gaseous, the reaction forms a “bubble” of etched silicon around the trenches. The shape of this bubble depends on the structure of the etched trenches and the spacing between them. Some of these configurations are shown in Figure 1. In this work, we analyze the etching of the silicon substrate using XeF_{2} for these configurations of trenches. Throughout this work, the circular, square and hexagonal trenches will be referred to as T1, T2 and T3 respectively. In case of T1, the XeF_{2} etch bubble consists of a semi-toroidal structure attached to a cylindrical structure as shown in Figure 2(a). The reaction is completely isotropic, hence it proceeds in all directions at the same rate. Thus, the depth to which the cylinder below the trench is etched is the same as the inner radius of the semi-toroid, say *x* (Figure 2(b)). If the diameter of the trench is *a*, the volume of the etched material at any time can be given by the sum of the volumes of the cylinder and semi-toroid as:

As the etch goes on, the value of *x* increases. When the etch bubbles from the adjacent trenches meet, the release of the silicon top layer is completed. Consider the distance between adjacent trenches to be *d*. Hence, from Figure 1, the value of *x* for a just completed etch can be obtained as

Hence, the volume per trench needed to be etched for a just completed silicon release is given by

This equation iscompletely dependent on the trench geometry and describes the volume of silicon to be etch for a just completed release. Let us consider a standard, room-temperature XeF_{2} etcher, with an expansion chamber of volume *V _{ch}* and expansion pressure of

*P*. Such a cyclic etcher introduces the expanded XeF

_{ch}_{2}gas into the etch chamber, allows some time for the reaction to complete, and then pumps down the chamber to remove the gas phase reactants before the next cycle of etch. Hence, in each cycle, the number of XeF

_{2}moles introduced in the chamber can be obtained from the ideal gas equation. These XeF

_{2}atoms consume silicon atoms in the ratio of 2:1 as shown in the chemical reaction in Equation (1). Hence, the silicon moles consumed per cycle are

These can be converted into loss of volume of silicon as

where *W* is the atomic weight of silicon and *ρ* is the density of silicon. This is the total silicon etched in a cycle. Hence, for *n* cycles, the total silicon volume consumed is

If the total number of trenches on the silicon area to be released are *N _{T1}*, the total volume to be etched can be equated to the volume etched for n cycles. Thus,

*V _{T1}* is given by Equation (4) and $ N T 1 =A/ d + a 2 $, where A is the total silicon area to be released. Thus,

Solving for the number of etch cycles, we obtain

From this equation, the number of cycles needed for releasing the top surface of a silicon piece can be obtained. The first term in the equation is a universal constant for silicon, the second term depends on the geometry of the XeF_{2} etcher tool, while the last term depends on the geometry of the silicon sample. During the cyclic etching process, the reaction may not complete due to the limited time provided for the reaction. Hence, not all of the moles of XeF_{2} may be consumed during a particular cycle. This can be mathematically represented by an “efficiency of the reaction” term, *η*. This number, between 0 and 1, represents the percentage of XeF_{2} used during a reaction. Indeed, a high value would be desirable to reduce the number of etch cycles. Hence, the final expression for the number of cycles can be written as

This equation can be greatly simplified if the geometry of the trenches is regular. Thus, if *d* = *a*, the expression can be written as:

In case of T2, the XeF_{2} etch bubble is a cuboid connected by four semi-cylinders on the four sides and four spherical surfaces on the edges. Thus, the volume of the etched bubble can be calculated as

The value of X for a just completed release in this case is $d/ 2 $. Also, the number of trenches per unit area is the same as T1 because the unit cell is still a square with sides (*d* + *a*). Thus, the number of cycles of XeF_{2} required for a compete release of area A is given by:

For *a* = *d*,

In case of T3, the calculation of the volume of etch bubble involves thirteen different regions, one hexagonal prism connected by six semi-cylinders on the sides and six spherical regions on the edges. The volume of the etched bubble per trench is expressed as:

For the etch to be just complete, the etch bubble needs to reach a point in the middle of three adjacent hexagons (as shown in Figure 1). This point is the center of the equilateral triangle formed by connected the three nearest vertices of the hexagons and the value of X in this case is $d/ 3 $. Also, the number of trenches per unit area in this case is different since the shape of the unit cell is no longer square. The unit cell is itself a regular hexagon with diameter, $ ( a + 2 d / 3 ) $. Hence, the number of trenches for a given area A can be calculated as

Hence, as in the previous equations, the number of cycles for full release is given by:

For *a* = *d*,

## III. AREA EFFICIENCY

If we compare the numerical constants for all the three cases (Equations (12), (15), and (19)), we may conclude that T3 is the most efficient way to place the trenches. This is because the etch cycles required for release in this case are much lower than T2, which in turn are significantly lower than T1. However, because the trench shapes and configurations are different, it is worth noting that the area consumed by these trenches on the silicon surface is different. This area is not useable for fabrication of electronic circuits, thus can be regarded as a price to be paid for making the silicon flexible. Hence, it is desirable to reduce the area required for making the trenches. We introduce a term called “area efficiency” of the trench design, which is a ratio of the area usable for fabrication of electronic circuits to the total silicon area. The area efficiency can be calculated for a unit cell by considering the area of one trench and the area of the unit cell. We report the area efficiency of the three designs under consideration as follows:

In the simple case of *a* = *d*, the area efficiencies for T1, T2 and T3 are calculated to be 0.804, 0.75 and 0.785 respectively. Thus, T1 is the most area efficient design, however takes the most time to release using the TPER process. On the other hand, T2 is the most area inefficient and does not even provide the best release. The best release time is provided by the honeycomb-inspired hexagonal trench design (T3), while the area efficiency is only slightly lower as compared to T1. Figure 3(a) illustrates the relationship between the designs and their area efficiencies. Further modifications of the designs can be done on the basis of unequal *a* and *d* values, by optimizing these values for either higher area efficiency or better release time as required by the application. In practice, the transistor layout in a particular integrated circuit (IC) is determined by the optimized interconnection and routing between the different components. In case of silicon ICs to be subjected to the TPER process for obtaining flexible ICs, we believe the place and route of silicon circuits will also be governed by the design of the trenches as an additional constraint. Hence, the area efficiency is an important parameter because it provides an insight into the “usable” area available to IC designers.

## IV. EXPERIMENTAL VERIFICATION

For the experimental verification of the theoretical predictions, we used the T1 design with *a* = *d* = *10 μm* (Figure 3(b)). The samples were prepared by lithographically patterning the trenches on oxidized silicon wafers, following by deep reactive ion etching (DRIE) up to 50 μm. The samples were then subjected to conformal atomic layer deposition (ALD) of 50 nm aluminum oxide (Al_{2}O_{3}) passivation layer at 300 °C. The Al_{2}O_{3} was anisotropically etched from the bottom of the trenches using reactive ion etching (RIE) with trifluoromethane (CHF_{3}) and argon plasma at 10 °C. The samples were then subjected to XeF_{2} release using Xactix X4 XeF_{2} etcher with an expansion chamber of 560 cm^{3} and 4 Torr expansion pressure. The process flow followed for release of silicon samples is schematically shown in Figure 3(c). The thickness of the silicon sample released using this process is dependent on the etch depth of the trenches. Higher trench depth results in higher average thickness of the released silicon. However, it should be noted that due to the nature of the XeF_{2} etch process, the backside of the released silicon sample has a “scalloping” structure which results in non-uniform thickness across the sample.

The etch distance, *x*, can be calculated for a given number of cycles from Equation (2) and (7). Figure 4(a) shows the graph of the etch distance for two different reaction efficiencies. The reaction efficiencies have been calculated from the observed etch distance for a given area to be etched. In case of the black curve, the area to be released was 12 cm^{2}. It was observed that the etch distance agreed closely with the theoretical model developed in this study and release was completed in around 90 cycles (Figure 4(b) and 4(c)). This corresponded to an etch efficiency of 0.21. When the area to be released was doubled (the red curve), we observed that the reaction efficiency also doubled. This is expected because the availability of a large silicon area enabled XeF_{2} to attack more silicon atoms during the limited cycle time. Thus, the efficiency was seen to double with the doubling of release area. However, this meant that the release again took the same number of cycles, around 90, to complete (Figure 4(d)). Hence, we can optimize the reaction efficiency by optimizing the area to be released, thus obtaining the least release time per unit area of silicon.

## V. CONCLUSION

We present the design criteria and a comprehensive mathematical model of the isotropic etching of bulk silicon (100) substrate using XeF_{2} gas etchant during the TPER process for obtaining flexible silicon. The analysis shows the most efficient way of structuring the trenches in terms of area and reaction time can be deterministically modeled. The analysis reported can be used to optimize an etch process based on the size and structure of the trenches to be used and the electronic circuits to be fabricated. The analysis is verified using experimentally released and partially released samples. We report that honeycomb-inspired hexagonal distribution of etch trenches provides the best release time (fastest etch), while a rectangular distribution of circular trenches provides the best area efficiency. Indeed, the techniques developed during this study can be applied to other geometries tessellating the 2D plane to compare release times and area efficiencies. The presented analysis can also be extended to other isotropic, gas-phase reactions taking place during bulk micro-machining of other substrates.

## ACKNOWLEDGMENTS

This publication is based upon work supported by the King Abdullah University of Science and Technology (KAUST).