On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO₂ thin film

Modern mobile computing including wearables and emerging Internet-of-Things (IoT) technologies such as smart sensor network demand extremely low power Large-Scale-Integration (LSI) systems.¹ Especially if the power is supplied by energy harvesting sources, ultralow power consumption as low as μW or less will be required for a chip to conduct data sensing, data processing, and data communication. At transistor level, the most effective way to reduce power consumption is lowering supply voltage (V_dd). However, if V_dd is lowered, drive current of the transistor is also reduced. If the drive current is reduced, the circuit delay is increased and off-state leakage current keeps flowing during the period, which is not desirable from the low power perspective. For mobile computing and sensor network applications, it is preferable for the device to become active and complete program tasks in the short time period, and then stand by in sleep mode for the rest of the time. Therefore, for the given program tasks, switching energy is an important metric for low power devices. In order to achieve energy-efficient switching at given V_dd, I_on/I_off needs to be as high as possible.² 

To increase I_on/I_off, it is commonly understood that subthreshold slope (SS) needs to be small. SS is generally expressed by SS = (∂Ψ_s/∂V_g)⁻¹(∂log₁₀I/∂Ψ_s)⁻¹, where Ψ_s and V_g are surface potential and gate voltage, respectively. The first term of the right hand side of the equation of SS represents the electrostatics of a metal-oxide-semiconductor (MOS) capacitor, meaning how efficiently V_g can bend the silicon band. On the other hand, the second term of the right hand side of the equation of SS represents the conductance, meaning how much current can be driven by the band bending. In the conventional MOS Field-Effect-Transistor (FET), ∂Ψ_s/∂V_g does not exceed one because of the voltage divider between the gate dielectric and silicon channel. The second term is ∼2.3kT/q because the transport in subthreshold region is dominated by diffusion transport of excess minority carriers, of which distribution is described by Boltzmann distribution, at the source side of the MOSFET. It is therefore known that SS has the minimum limit of 60mV/dec. To overcome the limit of 60mV/dec, there have been extensive researches to enhance the second term by employing novel steep-slope transistors such as tunneling FET (TFET)³ and impact ionization MOSFET (IMOS).⁴ However, TFET and IMOS have their own issues such as low drive current, complicated process flow, and necessity of modifying circuit layout for TFET, and high on-set lateral voltage, reliability issue, and complicated process flow for IMOS.

Then negative capacitance FET (NCFET) has been proposed by Salahuddin et al.,⁵ as an alternative steep slope transistor to overcome the classical limit of 60mV/dec, and has been extensively studied.^5–11 NCFET has the same structure as MOSFET except that ferroelectric thin film is used as a gate insulator. If ferroelectric material is used as a gate insulator, ∂Ψ_s/∂V_g can possibly exceed one because of the nonlinear characteristics of the ferroelectric, so called, negative capacitance. Negative capacitance has been, in fact, experimentally observed in ferroelectric thin film,¹⁰ which paves the new road to the innovative device technology. NCFET has the same electron transport mechanism of drift and diffusion as conventional MOSFETs, so that it can drive higher current than tunnel-based FETs thanks to the higher channel charge density brought by amplified Ψ_s at the same off-current. Therefore, NCFET has been attracting more interests because it has possibility to break the limit of SS = 60mV/dec and exceed the drive current of conventional MOSFETs. In addition, NCFET is a symmetric device with respect to source and drain upon device operation, which is beneficial in development and production of new device technology. Standard pull-up and pull-down CMOS logic circuits as well as pass-gate CMOS circuits which flow current in both directions between source and drain can be built by NCFET. It is not necessary to largely modify the logic circuit architecture and IP macro design from the conventional MOSFET.

Although NCFET is a promising candidate of a steep slope transistor, there had been obstacles in process integration. If conventional ferroelectric materials such as Lead Zirconate Titanate (PZT) and Barium Titanate (BTO) are used, the thickness of the gate insulator needs to be several hundreds of nanometer in order to balance the large polarization charge density and FET channel charge density, which is not compatible to advanced scaled Complementary MOS (CMOS) frond-end technologies. Moreover, the heavy metal contamination to the manufacturing line is also concerned.

Recently, ferroelectricity is discovered in Hafnium Oxide (HfO₂) based thin films by controlling crystalline phase of the films.^11–19 The ferroelectric HfO₂ thin film has been already applied to Ferroelectric Random Access Memory (FeRAM) using 28nm CMOS technology.¹⁹ If the ferroelectric HfO₂ thin film is used for NCFETs as well, the fabrication process will become fully CMOS compatible. NCFET can be one of the low-cost solution for IoT power requirement without relying on high-cost advanced CMOS technologies, because NCFET can be fabricated by any CMOS technology from the most advanced technologies to mature manufacturing technologies, just by introducing ferroelectric HfO₂ gate insulator process. In order to promote research and development of NCFET with ferroelectric HfO₂ for IoT application, it needs to be demonstrated that NCFET can be designed at ultralow supply voltage with ferroelectric HfO₂ as well as with the previously reported ferroelectric material.^5,6 A practical device design guideline to achieve sufficiently fast operation speed and reliable operation should be provided so that material parameters are appropriately selected for process development. Furthermore, it needs to be quantitatively estimated how much the energy per switching can be lowered by NCFET.

In this paper, to target sub-0.2V V_dd operation for ultralow voltage and ultralow power IoT application, we study practical device design for an energy-efficient NCFET with a ferroelectric HfO₂ gate insulator by tuning its material parameters, based upon physics-based numerical simulations, with respect to operation speed, material requirement, and energy efficiency. To verify the device design and its material requirement quantitatively, published ferroelectric HfO₂ data are extensively surveyed and referred to as practical parameter range. First, the operation principle of the NCFET is reviewed and its simulation method will be explained. Secondly, the simulation results will be shown and discussed with respect to the operation speed, material requirement, and energy efficiency. Finally, this work will be summarized.

As explained above, the structure of a NCFET is basically the same as a MOSFET, except that the gate insulator is replaced by a ferroelectric material as shown in Fig. 1. The basic operation principle of the NCFET is explained in Refs. 5 and 6. A ferroelectric MOS capacitor can be modeled by a series connection of a ferroelectric capacitance and a channel capacitance. Fig. 2(a) shows the ferroelectric polarization (P) - electric field (E) characteristics and channel charge as a function of V_g. In the ferroelectric MOS capacitor, the ferroelectric polarization charge density and the channel charge density should match. Therefore, a static operation point of the NCFET is determined by the cross-point of the P-E curve and the channel charge load line. The negative capacitance region is where the slope of the P-E curve is negative. If these two curves have a single cross-point in the negative capacitance region, the ferroelectric MOS transistor works as NCFET. The operation principle of NCFET can be also qualitatively understood from band diagram of NCFET. Fig. 2(b-i) shows the band diagram corresponding to the operation points of (i) in Fig. 2(a). As V_g is applied, a negative oxide field is induced on the gate insulator in the NCFET as opposed to conventional MOSFETs. As V_g is increased, the operation point moves to (ii) in Fig. 2(a), and the negative oxide field becomes even larger. The silicon band bends more than the applied V_g, that is ΔΨ_s/ΔV_g > 1 as shown in Fig. 2(b-ii). This means that the surface potential is effectively amplified against V_g, more channel charges are induced in the channel, and thus higher current is driven in the NCFET than in conventional MOSFETs. As V_g is even further increased, the operation point moves to (iii) in Fig. 2(a), and the oxide field flips and the band diagram looks the same as conventional MOSFETs as shown in Fig. 2(b-iii).

Next, the simulation method used in this work is summarized below. The ferroelectric MOS capacitor in the NCFET is modeled by series connection of the ferroelectric capacitance and the channel capacitance. The modeling and simulation method of ferroelectric MOS capacitor have been established in Refs. 5 and 6. The ferroelectric is described by the Landau-Khalatnikov equation,^5,6,20 which is a time-dependent phenomenological equation for ferroelectric materials,

where τ is the characteristics response time of the polarization and G is the Landau free energy. G is expressed by,

where α, β, and γ are Landau parameters.

In this work, the FET channel is described by the Poisson-Schrödinger equation to calculate electrostatics and quantum mechanical states. The simple ballistic transport model²¹ is used for the carrier transport in the NCFET.

In the simulation, first, a channel charge density is given. Then the Poisson-Schrodinger equation is solved to obtain the depletion charge density, inversion charge density, subband energies, surface potential and Fermi level. Next, the Landau-Khalatnikov equation is solved to obtain the oxide field. Then V_g is determined by adding the surface potential calculated by Poisson-Schrodinger equation and the voltage across ferroelectric gate insulator calculated by (1) and (2). Then the channel charge density is incremented and the calculation is repeated until the final target of the charge density or V_g is reached. The flatband voltage is arbitrarily chosen.

In order to constraint ourselves to realistic material parameters for practical device design, the literatures on the recent ferroelectric HfO₂ thin films were extensively surveyed to refer to. Fig. 3 summarized the representative material parameters such as remanent polarization (P_r) and coercive field (E_c). The data are distributed among 0<P_r<25μC/cm² and 0<E_c<2MV/cm. P_r = 9μC/cm² and E_c = 1MV/cm are about median values and chosen as reference material parameters of ferroelectric HfO₂.

For the reference material parameters, to find static operation points, the thickness dependence of Ψ_s-V_g characteristics of the MOS capacitor of the NCFET with ferroelectric HfO₂ was studied as shown in Fig. 4. V_g was swept back and forth, from negative voltage to positive voltage and vice versa. Ψ_s is certainly amplified without hysteresis in the thickness range of 3-5nm. This is an encouraging result because the thickness of the ferroelectric is just a few nm, which is preferable to the advanced scaled CMOS process integration. Moreover, only 0.2V V_g is needed to amplify Ψ_s, which enables low supply voltage operation. This result is comparable to previously reported Ψ_s-V_g characteristics^5,6 and thus ferroelectric HfO₂ can be regarded as a candidate for NCFET gate insulator material as well. 4nm is chosen as a reference thickness. Note that if the thickness is too thick, the static operation point is not properly set and the Ψ_s-V_g curve shows hysteresis.

First, the operation speed of NCFETs with ferroelectric HfO₂ is discussed to assess whether NCFET can satisfy speed requirement for microcontroller in IoT device. In general, the spontaneous polarization of a ferroelectric has a finite response time to an external field because it takes time for atoms to move from one site to the other site in the ferroelectric crystalline lattice. Therefore, the electronic characteristics of the ferroelectric has time dependence to the applied field. Fig. 5(a) shows the sweep time dependence of P-E curves of a ferroelectric Metal-Insulator-Metal (MIM) capacitor. The P-E curves show larger hysteresis for faster sweep and smaller hysteresis for slower sweep. If the sweep time is slow enough, the curve becomes close to the static P-E curve. Accordingly, Ψ_s-V_g curves of a ferroelectric MOS capacitor also show sweep time dependence as shown in Fig. 5(b). The Ψ_s-V_g curves show larger hysteresis for faster sweep and smaller hysteresis for slower sweep. If the sweep time is slow enough, the curve becomes close to the static Ψ_s-V_g curve. Therefore, this dynamic property of the ferroelectric can be another cause of the hysteretic behavior of NCFETs besides inappropriate static operation points, which was discussed in the previous section.

Fig. 6 summarized the hysteresis voltage of the Ψ_s-V_g curves with the x-axis of the sweep time normalized by the intrinsic response time of the spontaneous polarization. From this figure, if the response time is 10-100psec, the hysteresis voltage becomes less than 1mV and almost negligible. Thus the NCFET can operate at 1-10MHz with negligible hysteresis. Some literatures reported the response time as fast as 10-100psec.²² 1-10MHz clock speed is sufficiently fast for IoT sensor node device application. In order to investigate dynamic operation speed and also to establish precise device modeling, it is suggested to measure and characterize the intrinsic response time of the spontaneous polarization for ferroelectric HfO₂ by experiment.

Next, the material requirement for the design of highly energy efficient NCFETs is discussed. P_r and E_c can be changed by adjusting Landau parameters in our simulation. Fig. 7(a-i) shows the P-E curves at fixed E_c and variable P_r, while Fig. 7(a-ii) shows the P-E curves at fixed P_r and variable E_c. In both cases, the negative capacitance is certainly modulated by P_r and E_c. Fig. 7(b-i) and 7(b-ii) show the I_d-V_g characteristics of the NCFET corresponding to Fig. 7(a-i) and 7(a-ii), respectively. In all cases, the current slope of the I_d-V_g characteristics in NCFETs is modulated by changing the negative capacitance. Especially, the slope of the I_d-V_g characteristics is steeper above threshold rather than subthreshold region. In fact, I_d-V_g characteristics of P_r = 5μC/cm² and E_c = 0.75MV/cm shows the significantly steep slope less than 60mV/dec. It also appears that the subthreshold slope extends to the above threshold region.

In order to understand the steeper slope above threshold rather than in subthreshold region, Fig. 8 illustrates the relationship among Ψ_s, oxide voltage V_ox and V_g for each charge density. In the MOS capacitor, V_g-V_fb = Ψ_s + V_ox holds. The Ψ_s is amplified against V_g by accessing to the negative V_ox. Note that the charge density should match between the ferroelectric and the channel. In the MOS capacitor, the channel charge density is small (<10¹³cm⁻²) in subthreshold region and it increases by $Ψ s$⁠, while the channel charge density is high (>10¹³cm⁻²) in strong inversion region and it increases by exp(qΨ_s/2kT). To access the negative V_ox, the channel charge density should be sufficiently high to match ferroelectric polarization in strong inversion region rather than in subthreshold region. This is the reason that steeper slope is mainly observed above threshold region.

Based on this understanding, for low V_dd operation, a qualitative guideline for the choice of material parameters P_r and E_c can be described as follows, as well as Landau parameters:⁶ negative V_ox should be accessed at as low charge density as possible. For the fixed channel design, ferroelectric has to have low P_r to make the slope of the P-E curve smaller in the negative capacitance region. However, low P_r value means that the channel charge density to be balanced is also small, which results in low saturation drive current. In order to keep P_r but make the slope of the P-E curve in the negative capacitance region as small as possible, one possible way is to increase E_c. However, too large E_c causes too large negative V_ox, which, in turn, will not guarantee hysteresis-free operation point. Moreover, if E_c is too high when the NCFET accesses to negative V_ox in P-E curve, a large oxide field (>1MV/cm) is induced on the ferroelectric gate insulator. The ferroelectric gate insulator is then highly stressed and has a risk of electric breakdown. Therefore, the values of P_r and E_c need to be appropriately optimized for the steep slope operation at low supply voltage without hysteresis.

Then the material parameters P_r and E_c are quantitatively optimized for high energy efficiency in NCFET. The energy per switching is an important metric for energy efficiency. Since the switching energy of a transistor² is proportional to V_dd²(ξ + I_off/I_on), I_on/I_off is a simple metric that can be extracted from I_d-V_g characteristics. Therefore, I_on/I_off is plotted in P_r-E_c two-dimensional space and contour lines are drawn at different supply voltage to be targeted. Fig. 9(a) shows the V_dd = 0.5V case. The contour plot of the minimum slope of the I_d-V_g characteristics, which is defined in the same way as subthreshold slope, is also shown in the same graph. Note that the right-bottom region does not guarantee hysteresis-free operation as explained in the previous paragraph. From Fig. 9(a), high I_on/I_off can be obtained in the wide area in P_r-E_c space at V_dd = 0.5V. The material parameters can be chosen from this wide area for optimization. Fig. 9(b) shows the V_dd = 0.3V case. Although the I_on/I_off contour shifts to low P_r region, high I_on/I_off can be still obtained in the fairly wide area. Fig. 9(c) shows the V_dd = 0.2V case. Now high I_on/I_off can be obtained in the limited region in the P_r-E_c space around 0<P_r<5μC/cm² and 0.5<E_c<1MV/cm. In this region, E_c is low enough to avoid significant electronic breakdown of the ferroelectric gate insulator. For energy efficient design, material parameters should be chosen from this region.

Material parameters P_r and E_c were chosen from the high I_on/I_off region in Fig. 9(c), and corresponding I_d-V_g characteristics were shown in Fig. 10. For the design such as P_r = 2.5μC/cm² and E_c = 0.6MV/cm, high I_on/I_off ratio is certainly obtained in NCFET compared to the conventional MOSFET at drain-source voltage (V_ds) 0.2V. The switching energy is calculated with the optimum material parameters as a function of V_dd in Fig. 11. The V_dd at the energy minimum moves from 0.2V in the conventional MOSFET down to 0.18V in NCFET. The minimum energy is reduced and the energy efficiency is improved by 2.5 times. Referring to Fig. 3, there are existing material data of the ferroelectric HfO₂ thin films for the optimum P_r and E_c, and the material will be Si, Al or Zr-doped HfO₂. V_dd of the state-of-the-art CMOS technology is around 0.8V. If the supply voltage is lowered from 0.8V to 0.2V in the conventional MOSFET and then NCFET is used, the total energy efficiency is improved by about 10 times. Current commercial sensor node device consumes 10-100μW while energy harvesting technique using environmental energy source such as thermoelectric, vibration, and environmental radio or 10 year lifetime Li ion battery can supply 1-10μW. For given operation task, therefore, 10 times energy efficiency by NCFET should fill the gap between demand power and supply power of IoT device. The highly energy-efficient NCFET can contribute to sufficing the power requirement of IoT as a new CMOS platform.

A physics-based numerical simulator was built for NCFETs with the use of material parameters of ferroelectric HfO₂ gate insulator. The NCFET shows Ψ_s amplification with 3-5nm-thick ferroelectric HfO₂ gate insulator at low V_g<0.2V as well as previously reported ferroelectric materials. This thin ferroelectric HfO₂ enables NCFET to be fully compatible to the current CMOS process technology. NCFET can also operate at 1-10MHz with 10-100psec response time of the ferroelectric polarization. Negative capacitance was modulated by adjusting P_r and E_c, and then I_d-V_g was modulated by the negative capacitance. It was illustrated that steep slope appears above threshold rather than subthreshold region. By optimizing material parameters of ferroelectric HfO₂ gate insulator within the range of experimental material parameters, high I_on/I_off was obtained in the NCFET at V_dd 0.2V and the energy efficiency is improved by about 2.5 times compared to the conventional MOSFET.

This work is partly supported by New Energy and Industrial Technology Development Organization (NEDO).