Crystalline monolayers of CVD MoS2 are used as the active semiconducting channel in a split-gate field effect transistor. The device demonstrates logic AND functionality that is controlled by independently addressing each gate terminal with ±10V. When +10V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The ON/OFF ratio of the device was ∼ 35 and the charge mobility using silicon nitride as the gate dielectric was 1.2cm2/V-s and 0.1cm2/V-s in the ON and OFF states respectively. Clear discrimination between the two states was observed when a simple circuit containing a load resistor was used to test the device logic AND functionality at 10Hz. One advantage is that split gate technology can reduce the number of devices required in complex circuits, leading to compact electronics and large scale integration based on intrinsic 2-D semiconducting materials.

Bulk molybdenum disulfide (MoS2) is a naturally occurring layered transition metal dichalcogenide (TMD), consisting of atomically thin covalently bonded S-Mo-S planar structures with Van der Waals interaction between S-Mo-S planes.1,2 Monolayers can be obtained via exfoliation of macroscopic MoS2 crystals3–6 or via chemical vapor deposition (CVD) of selected Mo containing compounds in a gaseous sulfur rich environment.7–12 Pristine MoS2 is a n-type semiconductor typically characterized in a field effect transistor (FET) configuration with a global gate potential that is responsible for the transistor action. The charge mobility in these materials exceed 200 cm2/V-s for exfoliated MoS213–15 and ∼ 10 cm2/V-s for CVD grown MoS2 on SiO2 substrates.8,10,12 Being a stable n-type semiconductor, MoS2 has potentially wide range of applications in the fields of nano-electronics (FET, diodes) and energy harvesting (photovoltaics, solar cells). An important electronic device for practical applications is a FET, since it forms the basic building block in logic circuits and switches for displays and is thus widely studied using organic and inorganic semiconducting materials.

In a globally gated transistor shown in the schematic of Figure 1(a), the entire drain-source channel conductance is controlled by the common gate, and hence many such devices connected in tandem are required to fabricate simple logic circuits taking up un-necessary space. A split gate architecture is shown in Figure 1 (b) with a single drain-source channel, where individual gates that are independently addressed can be used to fabricate logic circuits that are more compact. In this work we report on the first fabrication and electrical characterization of monolayer MoS2 crystals as the active semiconducting channel in a split gate FET configuration. When both gates are simultaneously addressed “HIGH” the device turns “ON” while any other combination at the gate terminals renders the device “OFF”, resulting in a dual input logic AND operation. The ON/OFF ratio of the device was ∼35 and the charge mobility on the silicon nitride gate dielectric was ∼1.2 cm2/V-s in the ON state, limited in part due to the substrate topography and gate voltage swing. Since logic circuits with multiple inputs are widely used in devices such as comparators, the split gate configuration allows such functionality using a single transistor. By eliminating the need to cascade single input transistors, split gate technology can reduce the number devices required when designing logic circuits, leading to compact electronics based on TMD’s and large scale integration. While the split gate design should function for any bulk semiconductor in principle, the present work is aimed at demonstrating operation using intrinsic 2-D materials, thereby shifting the focus to low dimensional devices.

FIG. 1.

(a) Schematic vertical cross-section of a global gate field effect transistor showing the drain (D), source (S) and gate (G) terminals. (b) Schematic vertical cross-section of the split-gate field effect transistor showing the two gate terminals (G1 and G2) lying between the D and S terminals within the CVD grown silicon nitride (Si3N4) gate dielectric.

FIG. 1.

(a) Schematic vertical cross-section of a global gate field effect transistor showing the drain (D), source (S) and gate (G) terminals. (b) Schematic vertical cross-section of the split-gate field effect transistor showing the two gate terminals (G1 and G2) lying between the D and S terminals within the CVD grown silicon nitride (Si3N4) gate dielectric.

Close modal

The split gate device substrate was fabricated using chemical vapor deposition of the dielectric, combined with photolithography and lift off techniques for the electrodes, on commercially available Si/SiO2 wafers. It starts by fabricating the gate (G) electrodes on the as received commercial wafer, followed by CVD growth of a 100nm thick silicon nitride dielectric layer completely covering the gates, and finally followed by fabricating the source (S) and drain (D) terminals on either side of the buried gate electrodes.

Figure 2(a) is a top view optical microscope image of the substrate showing two FET electrode designs with a common source terminal and two drain terminals on either side of S. The gate electrodes (G1…G4) lie between the D and S terminals below the dielectric surface as evidenced by the color contrast in the image. Atomic Force Microscope images of the substrate reveal that the dielectric layer is conformal to the substrate, resulting in a non-planar surface between the S and D electrodes due to the buried gate electrodes.16,17 Windows are etched into the dielectric, permitting access to the gate electrodes for electrical contacts.

FIG. 2.

(a) Optical microscope (top view) image of a split gate substrate showing the source (S), drain (D) and gate (G) terminals prior to MoS2 transfer. (b) Top view scanning electron microscope image of the substrate in (a) after MoS2 (black stars) transfer. Windows are etched to gain access to the gate terminals. Electrical contacts are made on D, S, G1 and G2 for a typical device studied in this work.

FIG. 2.

(a) Optical microscope (top view) image of a split gate substrate showing the source (S), drain (D) and gate (G) terminals prior to MoS2 transfer. (b) Top view scanning electron microscope image of the substrate in (a) after MoS2 (black stars) transfer. Windows are etched to gain access to the gate terminals. Electrical contacts are made on D, S, G1 and G2 for a typical device studied in this work.

Close modal

Monolayer MoS2 crystals were fabricated using MoO3 via CVD in a sulfur rich environment on Si/SiO2 wafers and later transferred on to the split gate FET substrates.12,18 In a typical transfer process, the original substrate with MoS2 crystals is spun coated (4000 rpm/45 s) with PMMA and then immersed in a KOH (0.1M) solution. The SiO2 layer is slowly dissolved by KOH and the PMMA film with the MoS2 is washed with water and transferred on to the split gate FET substrate and dried. The PMMA film is then dissolved with acetone leaving MoS2 crystals making contact to the source and drain terminals of the device. A typical device after the transfer process is shown in Figure 2 (b), where more than one MoS2 crystal bridges the source and drain terminals.

Electrical characterization of the FET was done at room temperature in vacuum to avoid moisture effects. A Keithley Model 6517A electrometer connected to the S and D terminals supplied the drain-source voltage and measured the drain-source current, while two Keithley Model 2400 source meters were connected to the gate terminals that were addressed independently. For the dual gate operation, a SRS model DS335 synthesized function generator supplied AC excitation to the device at 10Hz and the output signals were recorded on an Agilent Technologies DSOX 2012A dual trace digital storage oscilloscope.

Figure 3 shows the drain-source current (IDS) versus drain-source voltage (VDS) of the split gate device with both gates (VG1 and VG2) simultaneously connected to the same voltage. When the gates are unbiased (0V), there is a linear increase in IDS as VDS is increased (black symbol curve), and is due to the intrinsic conductivity of MoS2. Applying a negative bias on the gates reduces the channel current (depletion mode) while a positive bias increases the current (enhancement mode) and is consistent with the n-type nature of the MoS2 semiconductor where the majority carriers are electrons. The ON/OFF ratio for this device calculated at VDS = 1.0V at extreme bias conditions of -10V or +10V on both gates was ∼ 35 and the unbiased intrinsic conductivity of the MoS2 channel was calculated to be 15 S/cm at room temperature. Increasing the gate voltage swing could improve the ON/OFF ratio, however, to prevent damaging the dielectric due to its topography we did not increase the voltage past ±10V. The upper inset to Figure 3 shows the device trans-conductance (IDS vs. VGS) curve for a fixed VDS = 50mV. The channel current increases with increasing gate bias, and is consistent with the data plotted in the main figure. From this plot the device trans-conductance (gm) can be calculated as follows:

gm=(IDSVGS)VDS=const
(1)

Assuming that the transistor has a common gate (VG1 = VG2) terminal, the slope of the linear portion of this curve was calculated to be 26 nS from which the charge mobility (μ) was determined from:

μ=gmLWCiVDS
(2)

where L is the channel length (40μm), W is the channel width (250μm), and Ci is the capacitance per unit area of the 100 nm thick silicon nitride layer (6.63x10−8 F/cm2 - assuming a dielectric constant of 7.5). Using the value of gm obtained above, the mobility was calculated to be ∼1.2 cm2/V-s. The average charge density n (electrons/cm2) in the channel is given by:

n=gmLqμW
(3)

where q = 1.6x10−19C is the electronic charge and was calculated to be 1.2x1010 cm−2 in the ON state. Substrate interactions (optical phonon scattering) and the non-planarity of the surface between the S and D electrodes16,17 could lead to associated defects, charge traps, and self-localization of charge, limiting the mobility. Nevertheless, the measured mobility is in the range measured by others on CVD grown MoS2 on SiO2 substrates and also supports the result that MoS2 is deformable and bendable within limits without degradation of its electronic properties.19 

FIG. 3.

Drain-source current (IDS) as a function of drain-source voltage (VDS) for a split gate MoS2 FET with the two gate voltages kept the same (i.e. VG1 = VG2) and varied from -10V to +10V in 2V steps in the direction of the arrow. Red: depletion mode; Blue: enhancement mode operation of the device. Inset: The device trans-conductance curve IDS versus VGS (=VG1=VG2) with VDS = 50mV constant. The slope of the line shown is the device trans-conductance (gm).

FIG. 3.

Drain-source current (IDS) as a function of drain-source voltage (VDS) for a split gate MoS2 FET with the two gate voltages kept the same (i.e. VG1 = VG2) and varied from -10V to +10V in 2V steps in the direction of the arrow. Red: depletion mode; Blue: enhancement mode operation of the device. Inset: The device trans-conductance curve IDS versus VGS (=VG1=VG2) with VDS = 50mV constant. The slope of the line shown is the device trans-conductance (gm).

Close modal

Figure 4 shows the device characteristic curves (IDS vs. VDS) when the gates are addressed independently. As seen in Figure 3, a higher OFF state is achieved with -10V applied to the gates rather than 0V. This could be lowered even further with higher negative bias but was not attempted in order to preserve the gate dielectric from damage. We have therefore used -10V as the logic 0 condition and +10V as the logic 1 condition to obtain a higher ON/OFF ratio. For each scan in Figure 4, the voltage on the gates could be either -10V or +10V permitting four possible combinations. As seen in Figure 4, at VDS = 1V, there is a significant output current only when both gates are simultaneously biased at +10V, any other combinations leads to a much smaller output current. This device therefore operates as a dual input logic AND gate. The inset to Figure 4 shows the device trans-conductance curves (IDS vs. VGS) for different gate bias combinations. The device trans-conductance is high only when both gates are biased with the same voltage, if one of the gates is held at -10V and the other allowed to vary, the trans-conductance is relatively small i.e. the device is in the OFF state. The charge mobility for the ON state was calculated as 1.2cm2/V-s and 0.1cm2/V-s for the ON and OFF states respectively.

FIG. 4.

Drain-source current (IDS) as a function of drain-source voltage (VDS) of the split gate transistor for the four possible gate voltage combinations VG1 and VG2 as indicated. Inset: The device trans-conductance curves IDS versus VGS with VDS = 50mV constant. Red: VG1 = VG2 = VGS; Green: VG1 = -10V (fixed) and VG2 = VGS; Blue: VG1 = VGS and VG2 = -10V (fixed).

FIG. 4.

Drain-source current (IDS) as a function of drain-source voltage (VDS) of the split gate transistor for the four possible gate voltage combinations VG1 and VG2 as indicated. Inset: The device trans-conductance curves IDS versus VGS with VDS = 50mV constant. Red: VG1 = VG2 = VGS; Green: VG1 = -10V (fixed) and VG2 = VGS; Blue: VG1 = VGS and VG2 = -10V (fixed).

Close modal

A simple application of the split gate device can be demonstrated via a dual input logic AND circuit shown schematically in the upper inset to Figure 5. The two gate contacts represent the input terminals of the device and the voltage tapped across a 24 kΩ resistor (R) connected to the source terminal and ground represents the output (VR). A 10Hz, 10V positive square wave signal was applied simultaneously to the gates as the input signal. Figure 5(a) shows the voltage waveform applied to the gate and Figure 5(b) shows the output voltage resulting from the four independently addressed gate bias conditions. When the two gates are each biased to the same voltage as plotted by VGS, there is a significant output voltage and the device is in the ON state with VR > 1V. In any of the other combinations, one or both of the gates was held fixed at -10V resulting in a reduced output voltage and the device is in the OFF state with VR < 0.3V. Clear discrimination between the ON and OFF states is thus observable in Figure 5(b). Higher ON/OFF ratios can be achieved via the fabrication of more planar substrates that would reduce the effects of scattering and by increasing the gate voltage swing, leading to enhanced mobility. As a simple model that explains this result, the split gates can be treated as being two gate voltage controllable switches connected in series, with the operation of the AND feature representing the ON or OFF states of these switches. The inset to Figure 5(b) represents the operating truth table for the split gate device. Similar devices with multiple gates can be similarly fabricated that could lead to more compact space saving electronics.

FIG. 5.

10V, 10Hz square wave response of the split gate field effect transistor captured on a dual trace digital storage oscilloscope. (a) Voltage applied to the gate terminals (b) Voltage recorded across the 24 kΩ resistor (VR). VDS was kept constant at +8V and the corresponding gate voltages were connected as follows. Red: VG1 = VG2 = VGS; Green: VG1 = -10V (fixed) and VG2 = VGS; Blue: VG2 = -10V (fixed) and VG1 = VGS; Pink: VG1 = VG2 = -10V (fixed). Inset (a) shows the schematic electrical connections to the device. If logic 0 represents the condition when a gate voltage is -10V and logic 1 represents the condition when a gate voltage is +10V, then the inset in (b) represents the truth table of the device, where A and B are the (gate) inputs and C is the output (VR).

FIG. 5.

10V, 10Hz square wave response of the split gate field effect transistor captured on a dual trace digital storage oscilloscope. (a) Voltage applied to the gate terminals (b) Voltage recorded across the 24 kΩ resistor (VR). VDS was kept constant at +8V and the corresponding gate voltages were connected as follows. Red: VG1 = VG2 = VGS; Green: VG1 = -10V (fixed) and VG2 = VGS; Blue: VG2 = -10V (fixed) and VG1 = VGS; Pink: VG1 = VG2 = -10V (fixed). Inset (a) shows the schematic electrical connections to the device. If logic 0 represents the condition when a gate voltage is -10V and logic 1 represents the condition when a gate voltage is +10V, then the inset in (b) represents the truth table of the device, where A and B are the (gate) inputs and C is the output (VR).

Close modal

A split gate field effect transistor using CVD MoS2 as the active semiconducting channel was fabricated and electrically characterized. This device operated as a dual input logic AND gate by individually addressing the gates with ±10V. Applying +10V simultaneously to the gates turns the device ON while any other combination of -10V or +10V turns the device OFF. When both the gates are addressed with +10V, the device operates as a regular FET with an ON/OFF ratio of ∼35 and the charge mobility was ∼1.2 cm2/V-s. Having planar substrates and increasing the gate voltage swing should increase these parameters, improving device performance. A simple circuit was designed and successfully tested at 10Hz to verify the logic AND functionality of the device. An essential feature of this architecture is that AND logic devices with multiple inputs can be fabricated with a single semiconducting channel. By eliminating the need to cascade single input transistors, split gate technology can reduce the number devices required to design complex logic circuits, leading to compact electronics and large scale integration based on intrinsic 2-D semiconducting materials.

This work was supported in part by NSF under grants DMR-PREM-1523463 and DMR-RUI-1360772.

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