The demonstration of the magnetic Ge metal-oxide-semiconductor field-effect transistor

As we known, the magnetic material has been developed a lot and used to form the nano-scale tunnel junction for the application of the advanced source and drain (S/D) design in the spin electronic device recently.^1,2 There have three main mechanisms to demonstrate the magneto-electric effect such as magnetostrictive, multiferroic, and surface anisotropy. Besides the useful application in the S/D region, the colossal magneto-capacitance effect,^3,4 which can benefit the transistor’s gate stack characteristics, has also been observed in our previous work⁵ by using the magnetic material as the metal gate (MG) in the metal-oxide-semiconductor capacitor (MOSCAP) two terminal device structure. We demonstrated that the magnetic FePt film as the MG can lead to the better Ge gate stack characteristics⁵ than other published methods such as plasma post oxidation technique,⁶ GeO_xN_y deposition,⁶ ZrO₂ deposition,⁷ and post NH₃/H₂ remote plasma treatment.⁸ In this work, the real three terminal transistor’s level data with the magnetic gate stack scheme is presented. The influence of the Ge transistor’s performance with the magnetic field along different directions such as the vertical and the lateral direction is also investigated.

Ring-type n-Metal-Oxide-Semiconductor Field-Effect Transistors (n-MOSFETs) were fabricated on the Ge (100) slightly p-type doped, ∼5 × 10¹⁴ cm⁻³ substrate. Wafers were first cleaned by diluted HF (1:50) and rinsed by deionized (DI) water. The BaTiO₃ high dielectric (HK) layer and the magnetic FePt MG film were processed in an ultra-high vacuum sputter system with direct current (DC) power and radio frequency (RF) power sources. The physical thickness (t_phy) of the BaTiO₃ HK layer and the magnetic FePt MG film is ∼80 nm and ∼100 nm, respectively. In this work, three different kinds of FePt MG films are used to investigate the colossal magneto-capacitance effect on the Ge FET including (1) the control FePt film without the magnetic field and the split FePt films with the intrinsic magnetic field along the (2) vertical/ (3) lateral directions (shown in the Fig. 1). The detailed process conditions including: pressure, power, heating temperature, and rotating speed for the deposition of BaTiO₃ HK layer and these three kinds of different FePt MG films are summarized in the Table I. Post deposition annealing (1150 °C, 10 minutes) was used on the BaTiO₃ HK layer to form the tetragonal phase, which has the higher intrinsic K value (∼178) and the better sensitivity for the K value improvement with the implement of the magnetic field.^5,9 Following the deposition of the HK/MG layers, lithography process and Cl plasma dry etching process were employed to define and pattern the gate stack region (channel length L_g = 10 μm). Wafers were then implanted with phosphorus (P⁺, 18 KeV, and 4 × 10¹⁵ cm⁻²) ions to form the self-aligned n⁺ S/D regions. Dopant activation anneal was done in N ambient at 420 °C. Finally, forming gas annealing was carried out at 300 °C.

The crystal structures on the BaTiO₃ HK layer and the magnetic FePt MG films are examined by x-ray diffraction (XRD), using Cu-Ka radiation at λ = 1.54056A. Rietveld refinement calculations are conducted using the Rietica software package based on the observed XRD pattern. In this work, the tetragonal phase BaTiO₃ dielectric is used as the HK layer, due to its higher intrinsic K value (∼178) and the better sensitivity for the K value improvement with the implement of the magnetic field. The measured XRD patterns for the BaTiO₃ HK layer and the magnetic FePt MG film can be referred to our previous module level work in Ref. 5. The Magnetic property measurements are conducted on a quantum design magnetic properties measurement system (MPMS) and 14 Tesla (T) physical properties measurement system (PPMS) equipped with a vibrating sample magnetometer (VSM). The electrical extraction on our device is carried out by using an Aglient 4294a impedance LCR analyzer.

Fig. 2 shows the measured metal resistivity and the extracted magnetic fields along the vertical/lateral directions on our three kinds of different FePt MG films (Fig. 1) for the study. The similar metal resistivity (∼19 Ω–μm²) among these three different FePt MG films makes the fair comparison on the transistor’s device performance. Based on the magnetic properties measurement, it shows that magnetic fields among the vertical/lateral direction are ∼0.2 T/∼0.03 T in the split FePt film, called as FePt MG film with the vertical magnetic field, while they are ∼0.04 T/∼0.21 T in the another designed FePt film, called as FePt MG film with the lateral magnetic field. In this work, we investigate the Ge gate stack characteristics (colossal magneto-capacitance effect) and compare the transistor’s device performance among those devices with three different kinds of FePt MG schemes (Fig. 1).

Fig. 3 and Table II show the Ge gate stack characteristics on the MG/BaTiO₃ HK layer/Ge MOSCAPs with and without the implementation of the magnetic FePt films as the MG, and benchmark our leading-edge result against other results. It shows that the thinner equivalent-oxide-thickness (EOT) about ∼0.75 nm reduction to 1 nm can be demonstrated by carrying out the magnetic FePt film with the intrinsic magnetic field (∼0.2 T) along the vertical direction as the MG. However, no obvious benefit can be observed when we use the magnetic FePt film with the intrinsic magnetic field (∼0.21 T) along the lateral direction as the MG. It indicates that the super Ge gate stack characteristic shown in the Fig. 3 is achieved by the inclusion of more generated dipoles in the BaTiO₃ HK layer with the coupling of the intrinsic built-in perpendicular/vertical magnetic field (∼0.2 T) from the designed FePt MG. Besides the improvement of EOT (∼0.75 nm reduction), gate leakage (Jg) is also found to be reduced ∼100X to ∼1.06 x 10⁻⁶ A/cm² due to the built-in electric field, resulted from the more generated dipoles, in the BaTiO₃ HK layer. The promising and leading-edge Ge Jg-EOT gate stack characteristics on our proposed magnetic gate stack scheme provide an advantage of the transistor’s performance improvement and a useful solution for the future high mobility Ge device design

Figs. 4 and 5 show the electrical characteristics on Ge n-FETs (L_g = 10 μm) with and without the implement of the magnetic FePt film with the intrinsic magnetic field (∼0.2 T) along the vertical direction as the MG. With the implement of magnetic gate stack scheme, EOT can be reduced ∼0.75 nm and Jg can be reduced ∼100X due to the colossal magneto-capacitance effect. These promising Ge Jg-EOT gate stack characteristics (Fig. 3) can further result in the ∼50% on-current (I_on) improvement shown in the Fig. 4 and the better sub-threshold swing (S. S) for the short channel control shown in the Fig. 5. Fig. 4 compares the experimental Id-Vg and Id-Vd curve with and without the implement of magnetic metal gate in the Ge n-FET under different voltage bias. Fig. 5 shows our device has the leading-edge short channel behavior due to the great gate stack characteristics.

In this work, we propose the magnetic gate stack scheme for the application of Ge n-FET. The magnetic gate stack scheme includes the tetragonal-phase BaTiO₃ dielectric as the HK layer and the FePt film with the intrinsic built-in magnetic field (∼0.2 T) along the vertical direction as the MG layer. With the demonstration of colossal magneto-capacitance effect in the real three terminal Ge transistor, the ∼75% EOT improvement, ∼100X Jg reduction, ∼50% I_on enhancement and the leading-edge S. S behavior for the short channel control are achieved. The promising transistor’s performance on the high mobility (Ge) material demonstrated in this work provides the useful solution for the future low power mobile device design.

This work is supported by National Science Council (NSC), Taiwan, under the Grant Nos. 101-2628-E-002-018-MY3 and 103-2221-E-002-215-MY3, and Ministry of Economic Affairs (MEA), Taiwan, under the Grant No. 103-EC-17-A-01-S1-219.