Band-to-band tunnel field-effect-transistors (TFETs) are considered a possible replacement for the conventional metal-oxide-semiconductor field-effect transistors due to their ability to achieve subthreshold swing (*SS*) below 60 mV/decade. This letter reports a comprehensive study of the *SS* of TFETs by examining the effects of electrostatics and material parameters of TFETs on their *SS* through a physics based analytical model. Based on the analysis, an intrinsic *SS* degradation effect in TFETs is uncovered. Meanwhile, it is also shown that designing a strong onset condition, quantified by an introduced concept - “onset strength”, for TFETs can effectively overcome this degradation at the onset stage, and thereby achieve ultra-sharp switching characteristics. The uncovered physics provides theoretical support to recent experimental results, and forward looking insight into more advanced TFET design.

## I. INTRODUCTION

Band-to-band tunnel FET is a promising candidate for next generation low-power digital applications, due to its low OFF-current and small subthreshold-swing compared to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). However, TFETs suffer from low ON-current mainly because of the large band-to-band tunneling (BTBT) barrier, especially for large band gap semiconductors including silicon, the material of choice for mainstream semiconductor technology. To overcome this shortcoming and further improve the subthreshold characteristics, many efforts^{1–11} have been focused on proposing new structures/materials for TFETs, among which several^{2–4} exhibit near perfect (step-like) switching characteristics, i.e., ultra-small *SS*. However, the hidden physics and design rules leading to such ideal subthreshold characteristics are still not apparent. As a result, certain degree of ambiguity prevails over the choice of structures and materials for achieving small *SS*, such as, which material system among Si, Ge and InGaAs has the greatest potential to reach the smallest *SS*. This work is aimed at exploring and understanding the physics behind these issues, based on which both theoretical and experimental results could be well explained, and more importantly, a general design rule for TFETs with small *SS* can be formulated.

## II. ANALYTICAL MODEL FOR SS

Within the Landauer's formalism, the current for one conduction mode in TFETs can be expressed as^{12}

where *q* is the electron charge, *h* is the Planck's constant, *T*(*E*) is the BTBT probability, and *f*_{s/d}(*E*) is the source/drain Fermi-Dirac distribution function. *E*_{vs} and *E*_{cc} (Fig. 1) are the valence band maxima in the source region and conduction band minima in the channel region, respectively. Fig. 1 shows the schematic illustration (top) of a double-gated n-TFET used as the sample device in this paper and the corresponding energy band diagram (bottom) along its channel surfaces. P-type source and n-type drain are highly doped, while the channel is left intrinsic. *W*_{T} is the minimum tunnel width, *E*_{vj} is the valence band maxima at the source/channel junction, *ΔE* is the allowed tunnel window contributing to transport, and *E*_{fs/d} is the source/drain Fermi level. Assuming *T*(*E*) remains constant across *ΔE*, it can be taken out of the integral in Eq. (1). This assumption is valid for BTBT in the range of small *ΔE* (within a few *kT*),^{13} which is the regime of essence for the *SS* physics of TFETs, as will be pointed out in the subsequent sections. In circuit applications, the drain voltage of an n-TFET is usually at least 0.1 V larger than the source voltage.^{5} This way, *f*_{d}(*E*) is small enough to be neglected compared to *f*_{s}(*E*). Thus, the source to channel tunneling current can be formulated as

where

*F*_{Integral} is the integral of the Fermi function part in Eq. (1). Note that the Fermi-Dirac distribution of electrons (in the source region, which is the relevant region in this work) is truncated by the band gap of the source region at *E*_{vs}.

To obtain the expression of *T*(*ΔE*), we need to solve the 2D Poisson's equation to obtain the channel potential. Simplifying 2D Poisson's equation into a 1D form as expressed in Eq. (4) by using Yan's parabolic approximation^{14} is an efficient approach in FET compact modeling.

where ϕ_{s} is the surface potential; *λ* is the natural length; *V*_{fb} is the flat band voltage; *ρ* is the charge density; and *ɛ* is the material permittivity. Following this approach, Zhang^{15} *et al.* recently developed an analytical model that can accurately capture the electrostatic potential profile around the tunnel junction in double-gated TFETs. Employing their model, *E*_{vj} can be expressed as:

where Δ*E*_{sc} = Δ*E* + δ*E* + *E*_{g}, *δE* (fixed at 0.1 eV in this work) is the value of *E*_{cc} - *E*_{vs} at *V*_{gs} = 0, and

where *N*_{a} is the source doping level; *ɛ*_{ch/ox} and *T*_{ch/ox} are the permittivity and thickness of channel material/gate dielectric, respectively.

The minimum tunnel width can be written as^{15}

where |$\lambda = \sqrt {\varepsilon _{ch} T_{ox} T_{ch} /(2\varepsilon _{ox})}$|$\lambda =\u025bchToxTch/(2\u025box)$

Tunneling probability is then calculated using the Wentzel–Kramers–Brillouin (WKB) approximation and the two-band dispersion relation,^{16}

where *m*_{T} is the tunnel effective mass, and |$\bar F$|$F\xaf$ is the junction electric field modeled as |$\bar F = E_g /W_T$|$F\xaf=Eg/WT$.

According to the definition, *SS* equals the gate voltage swing needed to change the drain current by one decade. Hence, combining Eq. (10) with Eq. (2), *SS* can be expressed as

where |$SS_T = \left( {\frac{{d\log _{10} \left( {T(\Delta E)} \right)}}{{d(\Delta E/q)}}} \right)^{ - 1},SS_{FD} = \left( {\frac{{d\log _{10} \left( {F_{{\mathop{\rm int}} egral} } \right)}}{{d(\Delta E/q)}}} \right)^{ - 1}$|$SST=dlog10T(\Delta E)d(\Delta E/q)\u22121,SSFD=dlog10F int egrald(\Delta E/q)\u22121$

Eq. (11) clearly shows the manner in which the tunneling probability variation and the truncated Fermi-Dirac distribution contribute to the total *SS* through *SS*_{T} and *SS*_{FD}, respectively. *SS*_{FD} can be easily expressed as,

The expression for *SS*_{T} can be written as,

where *ħ* is the reduced Planck's constant.

## III. EFFECT OF FERMI-DIRAC TRUNCATION

Before delving into the *SS* physics through the developed model, the transfer characteristics and *SS* behavior of a conventional Si TFET and a high-performance graphene-nanoribbon (GNR) based TFET are comparatively shown in Fig. 2. The purpose of showing this comparison is simply to point out the differences between the I-V curves of these two devices, and thereby serve as the starting point for the discussion on the *SS* behavior. The width and thickness of the GNR channel are 2.34 nm and 0.34 nm, respectively, while those of the Si channel are 1 μm and 10 nm, respectively. Other features of the two devices are kept identical. An in-house NEGF simulator^{17} and the Sentaurus device simulator^{18} are used to simulate the GNR and Si devices, respectively. Fig. 2 displays two main points that will be analyzed thereafter. Firstly, the *SS* of GNR TFET (red squares) approaches zero at some *V*_{g}, while that of the Si TFET (red triangles) does not. Secondly, the *SS* of GNR TFET increases much faster than that of Si TFET with *V*_{g}.

Fig. 3 shows the shapes of *SS, SS*_{T} and *SS*_{FD} versus *ΔE* for a double-gated Si TFET, calculated with Eqs. (11)–(13). Relevant parameters are listed in the caption of Fig. 3. When *N*_{a} is low enough so that *E*_{fs} is higher than *E*_{vs}, *SS*_{FD} expressed by Eq. (12) reduces to ln(10)*ΔE/q* as pointed out in Ref. 13. However, a high *N*_{a} required to achieve high ON-current usually pulls *E*_{fs} well below *E*_{vs} leading to a different *SS*_{FD} behavior as displayed in Fig. 3. According to the shape of *SS*_{FD} and its underlying physics, the *ΔE* range can be divided into three regions as notated by symbols I, II and III in Fig. 3. In region I (*0<ΔE<2kT,* the onset stage of TFETs), Eq. (12) reduces to

*SS*_{FD} exponentially approaches zero with decreasing *ΔE*, which stems from the truncation of the Fermi-Dirac distribution by the band gap of the source region (will be abbreviated as *Fermi-Dirac truncation* in following text). Starting from *ΔE* = 2*kT* to region II (2*kT <ΔE<E*_{vs}*-E*_{fs}) and then to region III (*ΔE> E*_{vs}*-E*_{fs}), *SS*_{FD} initially stays at a constant value of 60 mV/dec, and then quickly increases, which mimics the thermionic emission dominated subthreshold behavior of a MOSFET. Note that Eq. (11) can't describe the total *SS* in region II and III as accurately as in region I (the onset stage), which is the focus of this work. Calculated results in region II and III only provide a qualitatively correct trend of *SS*, as confirmed by the extracted *SS* shape in the numerical simulation in Fig. 2.

## IV. EFFECT OF OFF-CURRENT

Based on Eq. (14) and Eq. (11), all TFETs should have a near-zero *SS* within the onset stage due to their BTBT nature determined *Fermi-Dirac truncation*. The reason why a near-zero *SS* in simulated Si TFET does not appear is due to the fact that the OFF-current “immerses” the relatively low but quite sharply changing BTBT current within the onset stage, as schematically denoted (by red dotted curve) on the transfer characteristics curve for Si TFET in Fig. 2.

For a well designed/fabricated TFET, thermionic component of OFF-current is dominant and can be modeled as,

To bring out the near-zero-*SS* nature of TFETs, the BTBT current at the onset stage should be higher than the OFF-current. To quantify this effect, *I*_{onset} is defined as the BTBT current at *ΔE* = 0.5*kT* (∼13 meV). The concept of “onset strength” is proposed as the difference between *I*_{onset} and *I*_{off}. It is well known that the source doping level *N*_{a}, natural length *λ*, band gap *E*_{g} and tunnel effective mass *m*_{T} are the four critical parameters for TFETs performance.^{19} The former two can be classified as electrostatic parameters, while the remaining two as material parameters. We make these four parameters as variables in our study to lump the effect of several promising technologies, such as low-dimensional materials/structures, strain technology, III-V compound, etc. Fig. 4 shows the dependence of *I*_{onset} and *I*_{off} on these four parameters. As shown in Fig. 4(a), *I*_{onset} has a maximum value at a relatively high *N*_{a}. The initial increase of *I*_{onset} with *N*_{a} is due to the shrinkage of the tunnel width *W*_{T} leading to higher tunneling probability. However, when *N*_{a} increases too much, *E*_{fs} moves far below *E*_{vs}, leading to severely reduced occupation probability of states around the valence band edge of the source region and thus to the reduction of *I*_{onset}. *I*_{off} keeps decreasing with *N*_{a} because minority carrier density, which contributes to the OFF-current proportionally, decreases with *N*_{a}. When any of *λ, E*_{g} or *m*_{T} is reduced, *I*_{onset} is significantly enhanced as shown in Figs. 4(b)–4(d). The difference between the last three cases is that while *I*_{off} remains constant with *λ* and *m*_{T} variation, it keeps decreasing with increasing *E*_{g} (similar to *I*_{onset}). In other words, *N*_{a, λ} and *m*_{T} are the explicit parameters to enhance the “onset strength” and thus “pull” the steepest part of BTBT current above the OFF-current, while *E*_{g} is not explicit, since its effect on the “onset strength” depends on the rate of change of both the OFF-current and the BTBT current w.r.t *E*_{g} (Fig. 4(c)). There is, however, an exceptional condition in which *E*_{g} also becomes explicit. That is the hetero-junction TFET in which *E*_{g}, for *I*_{off} calculation, is the band gap of the source material, while for *I*_{onset} it is the band gap overlap between the source and the channel material. For this case, the red dashed line for *I*_{off} should be replaced by the blue horizontal dotted line (Fig. 4(c)).

It is worthwhile to note that the OFF-current of a not well designed/fabricated TFET should also include trap assisted tunnel leakage and gate leakage, which are not taken into account in Eq. (15). The trap assisted tunnel leakage may stem from interface states near the tunneling junction, defects at the tunneling junction (especially in hetero-junction TFETs), and high doping induced band edge states. These leakages will increase the OFF-current and somehow degrade the “onset strength” and prevent TFETs from exhibiting ultra-small *SS*. This issue needs further investigation but is beyond the scope of this article.

## V. INTRINSIC SS DEGRADATION IN TFET

In the TFET community, there exists an ambiguity^{19} about the minimum *SS* (*SS*_{min}) achievable for certain structure or material system. So far, it is clear that *SS*_{min} appears at the current level of *I*_{BTBT} = *I*_{off} (Fig. 2). For devices with strong “onset strength”, *SS*_{min} is apparently near-zero. However, strong “onset strength” usually requires stringent fabrication condition and thus is not easy to achieve. In this situation, to clarify the ambiguity, we need to extend the discussion from the contribution of *Fermi-Dirac truncation* to that of tunneling probability variation, i.e., *SS*_{T}. *SS*_{T} very close to *ΔE* = 0 does not play an important role, since the near-zero *SS*_{FD} there results in a near-zero *SS*, as reflected by Eq. (11). Therefore, a figure of merit−*SS*_{T@2kT}, which equals the value of *SS*_{T} at *ΔE* = 2*kT* is defined as an indicator of *SS*_{T} behavior. Fig. 5 shows the dependence of *SS*_{T@2kT} and *SS*_{min} on *N*_{a}, *λ*, *E*_{g} and *m*_{T}. When *N*_{a} increases, or *λ* (or *m*_{T,} or *E*_{g}) decreases, *SS*_{T@2kT} becomes larger. At first glance, these results seem unexpected, since the tunneling efficiency, which is a more familiar performance parameter for TFET, is expected to improve with higher *N*_{a}, or smaller *λ (or m*_{T} *or E*_{g}), i.e., “*I*_{on} improving condition”. Following analysis verifies that these results are physical. The two electrostatic parameters *N*_{a} and *λ*, determine the depletion widths *L*_{1} (Eq. (7)) in the source region, and *L*_{2} (Eq. (8)) in the channel region, respectively. When *N*_{a} becomes higher and/or *λ* becomes smaller, *L*_{1} and/or *L*_{2} shrink leading to the reduction of *W*_{T} according to Eq. (6). With higher *N*_{a} and/or smaller *λ*, *W*_{T} is smaller as expected. The important point is that the rate of change of *W*_{T} w.r.t *ΔE* also becomes smaller. This is because stronger electrostatic screening effect for devices with smaller *W*_{T} leads to slower rate of change of *W*_{T}., i.e., smaller *dW*_{T}/*dΔE*. Therefore, *SS*_{T} becomes larger for higher *N*_{a} or smaller *λ* according to Eq. (13). The manner in which the material parameters *E*_{g} and *m*_{T} affect *SS*_{T} is also clear from Eq. (13), but is governed by the nature of tunneling rather than the junction electrostatics, since Eq. (13) is directly derived from WKB approximation based tunneling probability expressed in Eq. (10). From the above analysis of *SS*_{T}, it can be deduced that these four parameters degrade (through *SS*_{T} in Eq. (11)) the *SS* in a manner that can be regarded as intrinsic properties of TFETs, and hence, the corresponding degradation in *SS* can be termed as *intrinsic SS degradation*. This effect is usually overlooked in the TFET community, but it plays an important role in determining the achievable *SS*_{min}.

## VI. PATHWAYS TOWARD MINIMUM SS

It can be observed from Fig. 5 that the effects of *N*_{a}, λ and *m*_{T} on *SS*_{min} are opposite of that on *SS*_{T@2kT}, while the effect of *E*_{g} displays the same behavior for both. The reason can be explained in a schematic manner as shown in Figs. 6(a) and 6(b). Compared to the reference condition (grey curves), both *I*_{BTBT} and *SS* in “*I*_{on} improving condition” (black curves) increase over the entire range of *ΔE*, due to the reduced tunnel barrier and *intrinsic SS degradation*, respectively. As analyzed above, the levels of *I*_{off} are critical in determining *SS*_{min}, since *SS*_{min} appears at *I*_{BTBT} = *I*_{off}. As shown in Fig. 4, *I*_{off} decreases with *N*_{a}, and remains nearly constant with *λ* (or *m*_{T}), while increases with *E*_{g}. Therefore, *I*_{BTBT} and *I*_{off} meet at much smaller *ΔE* (labeled as *ΔE*_{S}) than the original *ΔE* that corresponds to the reference condition (labeled as *ΔE*_{O}) for *N*_{a}, λ and *m*_{T} cases, while at relatively large *ΔE* (labeled as *ΔE*_{L}) (may be larger than *ΔE*_{O}) for the case of *E*_{g}. These trends lead to smaller *SS*_{min} for higher *N*_{a} or smaller *λ* (or *m*_{T}), while larger *SS*_{min} for smaller *E*_{g}, as shown in Fig. 6(b). In other words, the enhancement of “onset strength” with higher *N*_{a} or smaller *λ* (or *m*_{T}) overcomes the *intrinsic SS degradation*, leading to a reduction of *SS*_{min}, while that with smaller *E*_{g} is not strong enough to reach the same result. Several representative experimental results (*I*_{off} and *SS*_{min}) obtained recently on TFETs, are summarized in Fig. 6(c). The Si SOI device is set as the reference device, and improvements on specific parameters are denoted by corresponding arrows. It can be observed that using small-*E*_{g} channel materials, such as Ge and III-V, does not improve *SS*, because increased *I*_{off} degrades the “onset strength”, in agreement with the uncovered *SS* physics above. It is worthwhile to mention that *SS* of III-V devices may also suffer from interface traps, which is expected to improve with more advanced interface engineering in the near future. To increase ON-current while retaining small *SS*, hetero-junction TFET (with large *E*_{g} on source side for lowering leakage and small *E*_{g} or the band gap overlap of source and channel, for enhanced tunneling) could be a solution, which has been experimentally achieved to some extent in Ref. 6. Excellent electrostatics, arising from using nanowire structure, or using atomically-thin emerging 2D semiconducting crystals^{20–22} as channel materials, are also promising alternatives.

Thus far, the reasons for faster increase of *SS* of GNR TFET with *ΔE* compared to that for Si TFET, and the step-like transfer characteristics in many proposed TFETs^{2–4} can be well explained. Strong “onset strength” in these devices make their ultra-sharply changing BTBT current visible, i.e., larger than *I*_{off}, at the onset stage, leading to ultra-small *SS*_{min}. At the same time, the *intrinsic SS degradation* of these devices is also strong, i.e., *SS* increases rapidly with gate bias (i.e., *ΔE*), leading to quick flattening of the BTBT current, and thus to step-like transfer characteristics. From the application point of view, TFETs with strong “onset strength” should only be used for ultra-low power application in which supply voltages are ultra-low. The reason is that larger supply voltages result in larger regions (flattened part of BTBT current) degraded by *intrinsic SS degradation*. Thus the average *SS* over specific *I*_{d} or *V*_{g} (or supply voltage) interval will be increased, with reduced advantage of ultra-small *SS*_{min} at the onset stage.

## VII. SUMMARY

In summary, essential physics of the *SS* of TFETs is studied in this paper, from the perspectives of Fermi-Dirac distribution and tunneling probability variation. The novelty of this work can be attributed to the much improved insights gained into the *SS* characteristics of TFETs, wherein it is shown, by examining the effects of the four critical parameters for TFET performance - the source doping level, natural length, band gap and tunnel effective mass, that the truncation of the Fermi-Dirac distribution, OFF-current and the uncovered *intrinsic SS degradation* compete with each other and determine the minimum achievable *SS*. Detailed analysis suggests that small natural length, suitably high source doping level, and small tunnel effective mass, are preferred for homo-junction TFET design. On the other hand, for the hetero-junction TFET design, in addition to these three parameters, small band gap only at the tunnel junction (keeping band gap relatively large in the remaining areas to suppress OFF current) is preferred. The uncovered *SS* physics in this work is consistent with recent representative experimental results and offers the nanoscale device community deeper insight into TFET design.

This work was supported by the National Science Foundation, Grant No. CCF-1162633.

## REFERENCES

^{th}Device Research Conference (DRC)

^{rd}Berkeley E3S Symposium