Remarkable reduction in the threshold voltage of pentacene-based thin film transistors with pentacene/CuPc sandwich configuration

Organic thin film transistors (OTFTs) have attracted much attention because they are low cost, operate under low temperatures, are compatible with plastic substrates, and have much potential for application.^1–4 The development of high-performance OTFTs has progressed significantly; the mobility (>1 cm²/Vs) and on/off current ratio (>10⁵) of these OTFTs are comparable with those of amorphous silicon thin film transistors (TFTs).^5–8 In practice, however, OTFTs remain problematic in terms of the high threshold voltage (V_T; a few tens of volts).^7–10 To lower power consumption, low V_T is a basic requirement. Hence, methods to reduce OTFTs V_T have been developed, including the use of ultrathin or high dielectric constant insulators,^11–13 the improvement of metal/organic and organic/dielectric interfaces,^14–20 and the optimization of device configuration.^21,22 A previous study lowered the V_T of copper phthalocyanine (CuPc) TFTs from −13.8 V to −8.9 V using a double layer of active organic semiconductors of CuPc and cobalt phthalocyanine in sandwich configuration. This method produces low-V_T OTFTs conveniently despite the unclear rule regarding the selection of organic material pairs.²¹ In this study, we fabricate pentacene-based OTFTs with pentacene/CuPc sandwich configuration. In the process, we generate highly mobility, low-V_T devices. Furthermore, our proposed method is simple and effectively enhances the performance of pentacene-based OTFTs.

Fig. 1(a) shows the schematic of the pentacene/CuPc sandwich OTFTs. For comparison, we also fabricated pentacene OTFTs in top-contact configuration, as indicated in Fig. 1(b). We thermally grew 300 nm thick SiO₂ on a heavily doped n-Si wafer as a substrate. Initially, we deposited a 50 nm pentacene layer onto the substrates by vacuum deposition at room temperature. The deposition rate was 0.02 nm/s, and base pressure was 10⁻⁴ Pa. We then deposited 50 nm Au source/drain electrodes through a shadow mask. We partially shielded the pentacene film and Au electrodes (Fig. 1(b)). A CuPc film was deposited through another shadow mask on top of the film and the electrodes to generate devices with sandwich configuration. Using this fabrication procedure, we produced stable pentacene films. Moreover, we determined the influence of the OTFTs on sandwich configuration by comparing the performance levels of the pentacene/Au/CuPc (Fig. 1(a)) and pentacene/Au (Fig. 1(b)) devices. Channel length (L) and width (W) were 70 and 500 μm, respectively. All organic materials were purchased from Sigma-Aldrich and used as received. The electrical properties of the devices were measured by a semiconductor parameter analyzer (Keithley 4200-SCS) in a dark box under ambient atmosphere.

Fig. 2 illustrates the typical output and transfer characteristics of the top-contact pentacene-based OTFTs and the pentacene-based OTFTs configured with a 5 nm thick CuPc sandwich. The devices exhibited typical p-channel behavior under negative source-drain (V_d) and gate voltages (V_g), with distinct linear and saturation regions in the output curves. Comparing to the top-contact devices, the sandwich devices showed a significant increase of drain current (I_d) when V_d and V_g were constant. I_d increased by a factor of approximately 4.5 (from −37.4 μA to −168.2 μA) at V_d = −100 V and V_g = −100 V when a 5 nm CuPc layer was introduced into the pentacene/CuPc sandwich devices (Figs. 2(a) and 2(b)). Based on the transfer curves in Figs. 2(c) and 2(d), we determine the performance levels of the top-contact and sandwich pentacene-based OTFTs in terms of field-effect mobility (μ_FET), V_T, sub-threshold slope (S), and on/off current ratio (I_on/I_off). The V_T of the sandwich devices is negligible at −0.2 V. They also display a μ_FET of 0.51 cm²/Vs, S of 2.9 V/dec, and I_on/I_of of 4 × 10⁵. By contrast, the top-contact devices have a high V_T of −20.4 V, μ_FET of 0.18 cm²/Vs, S of 4.1 V/dec, and I_on/I_off of 1 × 10⁵. This result demonstrates that the introduction of a 5 nm CuPc layer enhances the electrical characteristics of pentacene/CuPc sandwich devices by reducing V_T and S and increasing mobility.

Fig. 3 exhibits the influence of CuPc thickness on the performance of sandwich pentacene-based OTFTs. The performance levels of seven sample devices are averaged, and the findings indicate that V_T and S gradually decrease when CuPc thickness increases from 0 nm to 5 nm. Correspondingly, μ_FET improves progressively with a slight increase in I_on/I_off. When CuPc layer thickness exceeds 10 nm, the performance of the sandwich devices declined, as indicated by the increased V_T and S and the reduced μ_FET and I_on/I_off. Given devices with a 20 nm thick CuPc layer, the values of V_T, μ_FET, S, and I_on/I_off are −19.5 V, 0.19 cm²/Vs, 4.0 V/dec, and 1 × 10⁵, respectively. These values are close to those of the top-contact devices. These results suggest that the performance of pentacene-based OTFTs was significantly enhanced when a thin CuPc layer (2 nm or 5 nm) was introduced. However, performance reverted to the original level when CuPc layer thickness exceeded these recommended values.

The enhanced performance of sandwich pentacene-based OTFTs could be attributed to the reduced charge trap density at the pentacene/dielectric interface. We estimated maximum interfacial trap density (N_trap) in both top-contact and sandwich devices using the following equation:^23,24

where C_i is the capacitance of the gate dielectric per unit area; q is the electronic charge; S is sub-threshold slope; k_B is Boltzmann's constant; and T is temperature. In the top-contact devices, the estimated N_trap is 5.1 × 10¹² cm⁻². After thin CuPc layers measuring 2 and 5 nm were introduced, the estimated N_trap dropped to 3.8 × 10¹² and 3.4 × 10¹² cm⁻², respectively. This finding indicated the remarkable decline in the number of interface trap states, which lowers V_T and S and enhances μ_FET. The estimated N_trap values of the sandwich devices are 4.1 × 10¹² and 5.0 × 10¹² cm⁻² given 10 and 20 nm CuPc layers, respectively. This result suggests that the number of trap states increased as a result of the thick CuPc layer. In the process, performance declines.

To understand the effect of the CuPc layer on the performance of pentacene-based OTFTs, which is dependent on layer thickness, we determined the evolution of the surface morphology of the organic film in CuPc-coated devices by atomic force microscopy (AFM), as shown in Fig. 4. The 50 nm thick pentacene film grown on SiO₂ substrates displays typical grains similar to polycrystalline terraces (Fig. 4(a)). After 2 and 5 nm CuPc layers were deposited on these grains, discrete small grains of CuPc gradually formed on the grains and the intergrain regions of pentacene films, as presented in Figs. 4(b) and 4(c), respectively. When CuPc thickness exceeded 10 nm, the small grains of CuPc enlarge, coalesce with one another, and eventually connect to form a layer of film that fully covers the pentacene film (Figs. 4(d) and 4(e)).

According to the combined results of electrical measurement, N_trap estimation, and morphology analysis, we propose the potential effect mechanism of the CuPc layer on sandwich devices. Previous studies suggest that the pentacene/dielectric interface contains thin intergrain regions, even in thick pentacene films with μ_FET values ranging from 0.1 cm²/Vs to 0.6 cm²/Vs. These regions constitute localized sites in which charges are trapped (Fig. 5(a)).²⁵ The high density of charge trap states either in the channel or at the semiconductor/dielectric interface induce high V_T and low S in top-contact, pentacene-based OTFTs.^26,27 The intergrain regions with high surface energy in pentacene films are the preferential areas for the CuPc deposition at early stages.⁹ By depositing 2 nm CuPc layer, small CuPc grains with electrical conductivity can partially bridge the pentacene grains and fill charge trapping sites in the intergrain regions of pentacene film (Fig. 5(b)), leading to the improvement of device performance. As increase the CuPc layer to a thickness of 5 nm, the charge trapping sites of pentacene films are nearly entirely filled by the CuPc grains (Fig. 5(c)), thereof, higher device performance is obtained. When the CuPc thickness exceeds 10 nm, continuous CuPc film formed on pentacene produces extra charge trapping sites and causes bulky resistance featuring the low conductivity of CuPc (Fig. 5(d)). As a result, charge transfer efficiency is reduced and device performance becomes poor. Besides, such a remarkable reduction of V_T of pentacene OTFTs was also observed by introducing a thin (2 E,2^′ E )-3,3^′-(2,5-bis(hexyloxy)-1,4-phenylene) bis(2-(5-(4-(trifleoromethyl)phenyl)thiophen-2-yl)acrylonitrile) (Hex-4-TFPTA) layer.¹⁷ While, the selection rule of organic semiconductors in sandwich configuration for reducing the threshold voltage of pentacene OTFTs is still open to debate.

Chen's report and our recent study had also demonstrated the improved performance of pentacene-based OTFTs using thin CuPc layers as buffer-layer and interlayer, respectively.^16,28 The enhanced μ_FET were obtained in devices with thin CuPc buffer-layer under the source/drain region (Fig. 5(e)), owing to the reduced carrier injection barrier between the Au source/drain electrodes and the pentacene active layer. However, V_T did not improve, potentially as a result of the almost unchanged charge trap density.²⁸ V_T and μ_FET decreased and increased, respectively, in devices that were completely covered with a thin CuPc interlayer (Fig. 5(f)). This finding could be attributed to the reduction in both carrier injection barrier and charge trap density.¹⁶ In the future, researchers may optimize the metal/semiconductor and semiconductor/dielectric interfaces for high-performance OTFTs by the selecting suitable materials and pattern regions.

In this study, we fabricate pentacene-based OTFTs with pentacene/CuPc sandwich configuration. The sandwich devices are significantly superior to conventional top-contact devices in terms of V_T, μ_FET, and S. For instance, V_T decreased sharply from −20.4 V to −0.2 V, μ_FET increased from 0.18 cm²/Vs to 0.51 cm²/Vs, and S was reduced from 4.1 V/dec to 2.9 V/dec. However, I_on/I_off remains constant at 10⁵. This enhancement could be ascribed to the reduction in charge trap density by the incorporation of the CuPc layer. This method is simple and effectively generates low-V_T and highly mobility pentacene-based OTFTs. Furthermore, it promotes commercial application of these transistors.

This work was financially supported by NSFC (21173114 and 61306021), NSFJS (BK20130579) and National Basic Research Program of China (973 Program, No. 2013CB932902).