Nanotip arrays with high aspect ratio, which have attracted much attention due to their potential applications, have been fabricated by many methods. Dry etching combined with self-assembly masks is widely used because of the convenience of dry etching and high throughput of self-assembly. In this paper, we report a method combining Cesium Chloride (CsCl) self-assembly with inductively coupled plasma (ICP) dry etching to fabricate silicon nanotip arrays with high aspect ratio and silicon nanotip arrays with aspect ratio 15 have been achieved after optimization of all parameters.
I. INTRODUCTION
Nanotip arrays with high aspect ratio have attracted much attention for their potential applications, such as field emitter,1 scanning electrochemical microscopy,2 ion mobility spectrometer,3 Scanning Probe Microscopy,4 MEMS,5 and so on. The fabrication methods mainly contain vapor-liquid-solid growth,6 metal-assisted chemical etching,7 and dry etching combined with self-assembly masks. Dry etching combined with self-assembly masks is widely used because of the convenience of dry etching and high throughput of self-assembly.8
There are four types of self-assembly masks: metal, nanospheres, copolymer, and deliquescent salts. Metal nanodots (Ag)9 can easily contaminate substrates and are hard to remove, diversified inorganic (silica)10 and organic (colloids)11 nanospheres tend to agglomerate, copolymer micells’12 diameter is limited, while deliquescent salt masks have the advantages of easy mask removing, high etch selectivity, high coverage, wide diameter range and compatibility. CsCl is one of such deliquescent salts and it's easy to acquire.13
Dry etching is one kind of micro-manufacturing technology. It's currently used in semiconductor fabrication processes due to its unique ability over wet etch to do anisotropic etching.14 It generally contains ion beam etching (IBE), reactive ion etching (RIE) and ICP. ICP is widely used in fabricating a high aspect ratio structure for the following reasons: (1) The plasma density of ICP is on the order of 1015 cm−3 which is much more than that of IBE and RIE; (2) Two independent RF powers make it easy to achieve more anisotropic etch profiles.15
In this paper, we report a method combing CsCl self-assembly with ICP dry etching to fabricate silicon nanotip arrays with high aspect ratio. CsCl is used to form self-assembly masks on a silicon wafer and then ICP is used to transform the CsCl self-assembly masks into silicon nanotip arrays. The optimization of the parameters in the process is studied in detail.
II. EXPERIMENTS AND METHODS
The substrates are 2 inch silicon (001) wafers with single side polishing. The first step is cleaning the silicon wafer: The wafer is put into concentrated sulfuric acid in a quartz kettle and is heated, kept boiling for 10 minutes. When the concentrated sulfuric acid cools down, the silicon wafer is put into the deionized water and the heating step is repeated, kept boiling for 10 minutes. After that, the wafer is dried with nitrogen. CsCl is thermally evaporated on the clean wafer to develop self-assembly masks, which are called CsCl nanoislands in the following text, in wet air by controlling CsCl film thickness, air relative humidity, developing time, and temperature. After CsCl nanoislands are developed, the silicon wafer must be moved into a dry etching chamber or kept in a dry box in a timely fashion because CsCl nanoislands can easily conglutinate under exposure to wet air. In a dry etching chamber, CsCl nanoislands are transformed into high aspect ratio silicon nanotip arrays under appropriate conditions including the gas species and flow rate, excitation power, bias power, chamber pressure, and etching time, all of which will be discussed in that order in the next part. After dry etching, some residual CsCl nanoislands are removed by rinsing in deionized water. The process of CsCl self-assembly and dry etching are shown in Fig. 1(a) Form CsCl islands on a silicon wafer; (b) Dry etching by ICP; (c) Removal of residual CsCl on silicon wafer. At last, all the silicon wafers are cut into small pieces in order to record the nanotip's morphologies by SEM.
The process of CsCl self-assembly and dry etching. (a) Form CsCl islands on silicon wafer; (b) Dry etching by ICP; (c) Removal of residual CsCl on silicon wafer.
The process of CsCl self-assembly and dry etching. (a) Form CsCl islands on silicon wafer; (b) Dry etching by ICP; (c) Removal of residual CsCl on silicon wafer.
III. RESULTS AND DISCUSSION
A. CsCl nanoislands
The process of forming CsCl nanoislands is as follows: Firstly, CsCl film is coated on silicon wafer by thermal evaporation. Then it is exposed to wet air with different relative humidities for different times to develop CsCl nanoislands with diverse diameters and packing densities. The process flow is shown in Fig. 2(a) the CsCl film is thermally evaporated on a silicon wafer; (b) the CsCl film absorbs water from the substrate and becomes discontinuous because of surface tension; (c) the discontinuous CsCl film absorbs water from the wet air and forms a blocky structure; (d) the blocky structure further absorbs water from the wet air and finally formsa structure made up of hemispheres when the surface tension reaches a minimum. Fig. 3 shows two kinds of CsCl nanoislands’ SEM photographs that will be used as dry etching masks and the detailed parameters of the process conditions are listed in Table I.
Process of forming CsCl nanoislands: (a) thermal evaporation of CsCl film on silicon wafer; (b) discontinuous film formed by substrate moisture; (c) CsCl blocky structure formed by absorbing water from wet air; (d) CsCl hemisphere structure formed by further absorbing water from wet air after the surface tension reaches a minimum.
Process of forming CsCl nanoislands: (a) thermal evaporation of CsCl film on silicon wafer; (b) discontinuous film formed by substrate moisture; (c) CsCl blocky structure formed by absorbing water from wet air; (d) CsCl hemisphere structure formed by further absorbing water from wet air after the surface tension reaches a minimum.
(a) nanoislands formed from 200 nm CsCl film with average diameter 396 nm and package density 27%. (b) nanoislands formed from 360 nm CsCl film with average diameter 521 nm and package density 30%.
(a) nanoislands formed from 200 nm CsCl film with average diameter 396 nm and package density 27%. (b) nanoislands formed from 360 nm CsCl film with average diameter 521 nm and package density 30%.
Process conditions of two kinds of CsCl nanoislands in Fig. 3.
. | CsCl film thickness (nm) . | Relative humidity (%) . | developing time (min) . | temperature (°C) . |
---|---|---|---|---|
(a) | 200 | 40 | 30 | ∼23 |
(b) | 360 | 50 | 50 | ∼23 |
. | CsCl film thickness (nm) . | Relative humidity (%) . | developing time (min) . | temperature (°C) . |
---|---|---|---|---|
(a) | 200 | 40 | 30 | ∼23 |
(b) | 360 | 50 | 50 | ∼23 |
B. ICP etching
1. Etching gas species and flow rate
The gases we use are SF6, C4F8 and He. SF6 forms activated fluorine radicals under high frequency glow discharge and the fluorine radicals will react with silicon to generate SiF4, a kind of gas which can be removed by the exhaust system with the aim of etching the silicon. C4F8 plays the role of a passivator. It will form polymers on the surface of the exposed silicon wafer to prevent further etching by the SF6. He flows underneath the silicon wafer and is used to reduce the temperature. By using these gases, we can etch the silicon quickly, stably, and anisotropically. Based on our experience, the flow rates of C4F8/SF6 /He are chosen to be 80/40/10 sccm because the morphology under this condition is very straight and steep.
2. Excitation power
Excitation power mainly affects the plasma density in the chamber. In order to investigate the influence of the excitation power on the morphology of the silicon nanotips, we etch the silicon wafer with coated CsCl nanoislands, shown in Fig. 3(a), for 5 minutes under varied excitation powers, 800 W, 400 W and 200 W, while keeping the bias power and chamber pressure at 5 W and 3.5 Pa, respectively. As illustrated in Fig. 4, 800 W is so high that the morphologies of the silicon nanotips are squamae. It's hard to control the etching structure. The morphologies of the silicon nanotips etched under 400 W are dots. It's also hard to precisely control the structure. 200 W is suitable, because the morphologies are truncated cones. It can be etched into tips with the increase of etching time. 100 W still works, but the etching rate is much slower than at 200 W.
Morphologies of silicon nanotips etched under different excitation powers: (a) 800 W, squamae; (b) 400 W, dots; (c) 200 W, truncated cones. All with fixed bias power 5 W, chamber pressure 3.5 Pa, etching time 5 minutes. All the pictures were photographed with tilt angle 45º.
Morphologies of silicon nanotips etched under different excitation powers: (a) 800 W, squamae; (b) 400 W, dots; (c) 200 W, truncated cones. All with fixed bias power 5 W, chamber pressure 3.5 Pa, etching time 5 minutes. All the pictures were photographed with tilt angle 45º.
3. Bias power and chamber pressure
After determining the optimal excitation power, 200 W, the bias power (BP) and chamber pressure (CP) need to be optimized. These two parameters play an important role in changing the vertical etching rate (VER) and the lateral etching rate (LER). The ratio of VER to LER is significant, because a silicon nanotip's aspect ratio increases with an increase of the ratio of VER to LER. Through measuring the VER, LER and calculating the ratio of VER to LER, the optimal bias power and chamber pressure to fabricate a silicon nanotip with high aspect ratio will be determined. Bias power is first optimized and excitation power, chamber pressure and etching time are fixed at 200 W, 3.5 Pa, 5 min, respectively. The VER and LER under different bias powers are shown in Fig. 5(a). The VER keeps increasing with increasing bias power, while the LER first reduces, and then increases with increasing bias power. At BP = 10 W, the LER reaches a minimum and the ratio of VER to LER reaches a maximum. In the same way, fixing the excitation power at 200 W, the bias power 10 W, and etching time 5 min, the VER and LER under different chamber pressures are shown in Fig. 5(b). The VER keeps decreasing with increasing chamber pressure, while the LER first reduces, and then increases with increasing chamber pressure. At CP = 3 Pa, the LER reaches a minimum and the ratio of VER to LER reaches a maximum at the same time.
(a) Influence of bias power on etch rate with fixed excitation power 200 W, chamber pressure 3.5 Pa and etching time 5 min. The ratio of VER to LER reaches a maximum at 10 W. (b) Influence of chamber pressure on etch rate with fixed excitation power 200 W, bias power 10 W and etching time 5 min, the ratio of VER to LER reaches a maximum at 3Pa.
(a) Influence of bias power on etch rate with fixed excitation power 200 W, chamber pressure 3.5 Pa and etching time 5 min. The ratio of VER to LER reaches a maximum at 10 W. (b) Influence of chamber pressure on etch rate with fixed excitation power 200 W, bias power 10 W and etching time 5 min, the ratio of VER to LER reaches a maximum at 3Pa.
4. Etching time
The last parameter to be optimized is the etching time after determining the optimal excitation power to be 200 W, bias power 10 W and chamber pressure 3 Pa. The silicon wafers coated with CsCl nanoislands shown in Fig. 3(a) are etched for 15 min, 20 min, 25 min and 30 min. It is worth mentioning that the ICP etcher must stop to rest for 5 min when it has worked over 5 min because a large amount of heat is generated and this can impact the ICP's stability. The morphologies of these silicon nanotips were photographed by SEM. As shown in Fig. 6, 15 min is too short since the morphology is still a truncated cone, while 25 min and 30 min are too long because some nanotips are etched off. 20 min is more appropriate since the nanotip is sharp and steep. For the silicon wafers coated by the CsCl nanoislands shown in Fig. 3(b), the corresponding etching time was studied and 25 min was finally found to be optimal.
Silicon nantips etched with CsCl nanoislands masks shown in Fig. 3(a) for different etching times: (a) 15 min (b) 20 min (c) 25 min (d) 30 min, of which 20 min is appropriate. All the pictures were photographed with tilt angle 45º.
Silicon nantips etched with CsCl nanoislands masks shown in Fig. 3(a) for different etching times: (a) 15 min (b) 20 min (c) 25 min (d) 30 min, of which 20 min is appropriate. All the pictures were photographed with tilt angle 45º.
Fig. 7 shows details of the silicon nanotips fabricated with the CsCl nanoislands shown in Fig. 3. as masks. Fig. 7(a): The masks are the CsCl nanoislands in Fig. 3(b), and the ICP etching condition is excitation power 200 W, bias power 10 W, chamber pressure 3 Pa, etching time 25 min. The nanotips’ height is 1.6 μm, and the aspect ratio reaches 15; Fig. 7(b): The masks are the CsCl nanoislands in Fig. 3(a), and the ICP etching condition is excitation power 200 W, bias power 10 W, chamber pressure 3 Pa, etching time 20 min. The nanotips’ height is 1.0 μm, and the aspect ratio reaches 13. The differences between the two photographs are the CsCl nanoislands’ size and etching time. The average diameters of the CsCl nanoislands in Figs. 3(a) and 3(b) are 396 nm and 521 nm. The bigger the CsCl nanoislands are, the longer etching time they can bear.
(a) Silicon nanotips etched for 25 min with the CsCl nanoislands masks in Fig. 3(b) under the conditions of excitation power 200 W, bias power 10 W, chamber pressure 3 Pa.The height is 1.6 μm and the aspect ratio reaches 15. (b) Silicon nanotips etched for 20 min with the CsCl nanoislands masks in Fig. 3(a) under the conditions of excitation power 200 W, bias power 10 W, chamber pressure 3 Pa. The height is 1.0 μm and the aspect ratio reaches 13. All the pictures were photographed with tilt angle 45º.
(a) Silicon nanotips etched for 25 min with the CsCl nanoislands masks in Fig. 3(b) under the conditions of excitation power 200 W, bias power 10 W, chamber pressure 3 Pa.The height is 1.6 μm and the aspect ratio reaches 15. (b) Silicon nanotips etched for 20 min with the CsCl nanoislands masks in Fig. 3(a) under the conditions of excitation power 200 W, bias power 10 W, chamber pressure 3 Pa. The height is 1.0 μm and the aspect ratio reaches 13. All the pictures were photographed with tilt angle 45º.
IV. CONCLUSIONS
The process of fabricating silicon nanotip arrays with high aspect ratio by CsCl self-assembly and ICP dry etching has been investigated. The ratio of the vertical etching rate to the lateral etching rate can be precisely controlled through optimizing parameters including the gas species, flow rate, the excitation power of the inductively coupled plasma (ICP) etcher, the bias power, and the chamber pressure. In addition, silicon nanotip arrays with aspect ratio of 15 have been successfully achieved under the conditions of CsCl nanoislands’ average diameter 521 nm, C4F8/SF6/He flow rates 80/40/10 sccm, excitation power 200 W, bias power 10 W, chamber pressure 3 Pa, and etching time 25 min.
The CsCl is easy to acquire and a CsCl self-assembly mask can be easily formed on silicon wafers with a simple process. The ICP dry etching process is also simple to operate, the whole processing cycle takes generally a few hours. Therefore, this method is simple, fast, and effective in fabricating silicon nanotip arrays over a large area and we believe it will be helpful in fabricating other micro-nano structures.