Miniaturized overlapped LC phase delay line Open Access

Because of its low loss, high linearity, wide-band characteristics and low cost, the microelectromechanical system (MEMS) distributed phase delay line (PDL) has been intensively investigated for use as the core phase-tuning structure in true-time delay (TTD) devices for phased array radar, electronic warfare, remote sensing and communication systems applications.^1,2 Traditional MEMS delay lines have mainly been designed based on a simple distributed transmission line and phase tuning has been realized by varying the length of the line.^3,4 However, the line length will constantly increase as the required phase shift grows, which leads to undesirably large areas being occupied by the structure. Because radar and communication systems contain large numbers of TTD devices, they present increasing demands and challenges for the design of miniaturized and low-loss PDLs. Several approaches have been proposed to reduce the size of TTD devices, including optimization of the location configuration of the phase delay units in the system,^5,6 or the use of microstrip transmission lines and metal-insulator-metal capacitors to form lumped LC circuits.⁷ However, no research literature has been published to date with regard to the reduction of the delay line itself, which is a critical factor in determination of the total device size.

In this paper, a novel compact LC PDL design based on overlapped meander inductors and air-bridge capacitors is presented. The miniaturized structure directly reduces the delay line size by replacing the transmission line with a meander inductor. 45º and 90º PDLs were designed using a semi-lumped model, and the device parameters were calculated and optimized based on transmission line theory and 3D simulations. The fabricated devices reduced the size of the delay line by 50% and show excellent radiofrequency (RF) performances across the entire DC–35 GHz operating band.

Based on coplanar waveguide (CPW) structures, the miniaturized overlapped LC structure consists of a meander inductor and an air-bridge capacitor, as shown in Fig. 1. Rather than spiral-type inductors (e.g. square, octagonal, or circular), the meander type inductor was chosen because of its simpler fabrication process using two-dimensional shapes. The inductor replaces and functions as part of the CPW signal line. The air-bridge capacitor was realized based on a suspended beam anchored to the ground plane of the CPW. The beam and the meander inductor comprise an air quasi-parallel plate capacitor. The complete compact structure can be fabricated by standard MEMS processing.

A semi-lumped equivalent circuit model is proposed in this paper for investigation of the electrical properties of the LC delay line, as shown in Fig. 2. The two-port network is symmetrical and consists of three parts, Z_CPW, Z_Lm and Z_Cair, which correspond to the CPW, the meander inductor and the air-bridge capacitor, respectively. The electrical and structural parameters were primarily obtained based on transmission line theory (using MATLAB) and 3D extraction (using HFSS). Then, the final parameters are determined by synthetic simulation and optimization (using ADS).

Figure 3 shows a schematic view of the air-bridge capacitor. At the 1-1 section, the structure is equivalent to a microstrip structure, where the bridge is the metal conductor, the CPW signal line is the ground plane, and the air gap is the microstrip substrate. At the 2-2 section, however, the capacitor can be equivalent to an upside-down microstrip. In this case, the CPW substrate becomes the upper medium, the CPW signal line becomes the metal conductor, the bridge becomes the ground plane, and the air gap still represents the microstrip substrate.⁸ 

The total capacitance C_total contains two components: a parallel plate capacitance, C_p, and a fringing capacitance, C_f.

The well-known equation for the parallel plate capacitance C_p is

where ɛ₀ is the vacuum permittivity, w is the width of the signal line, S is the width of the metal bridge and h is the gap between the bridge and the signal line.

The fringing capacitance C_f can be described using

where c is the speed of light in free space, Z_L0 is the characteristic impedance of the microstrip line, W_eq0 is the equivalent width when the thickness of the metal t>1 and the relative dielectric constant ɛ_r = 1. Z_L0 is given by

where F₁ can be obtained from

and W_eq0 can be calculated using

where t is the metal membrane thickness. Z_L1 and W_eq1 can also be obtained using the same equations, (4)–(6), by replacing w and t_bridge with S and the CPW thickness, respectively.

Figure 4 shows the basic structure of a meander inductor and its parameters are annotated. Because the inductor is a part of the signal line, the inductor thickness t_l is equal to that of the CPW. When the total length of the meander inductor w is determined, the required inductance can be obtained by tuning a, d, h_l, and the number of turns N_l.

The widely accepted Π model⁹ is applied to describe the equivalent circuit of the inductor, as shown in Fig. 4. Z_Lm is divided into two equal parts on each side of C_air. L_m is the effective inductance, R_m represents the intrinsic loss, and C_s and R_s are parasitic capacitance and resistance values, respectively, and are induced by the substrate. All values were extracted based on the S parameters from HFSS simulation, as follows:

In this design, all structures were fabricated with gold for optimized RF performance. The CPW was impedance-matched to 50 Ω at 35 GHz and W/S/W was equal to 15 μm/120 μm/15 μm. The thicknesses of the CPW, the bridge and the inductor were all 2 μm, and the air gap of the capacitor was 3 μm. The width of each line of the inductor w_l was 10 μm. The width of the capacitor (and also the total length of the meander inductor) w was initially set to meet the size reduction requirements. First, C_air was calculated based on Eqs. (1)–(6), and thus the numerical ranges of L_m, R_m, C_s and R_s were determined. Then, the structural parameters (a, d, h_l, and N_l) of the meander inductor were tuned accordingly, with their extraction based on Eqs. (7)–(9). In this way, the 45º and 90º PDLs can be realized from the synthetic simulation of the equivalent circuit.

The optimized parameters are summarized in Table I and Table II. Compared with the equivalent conventional transmission lines, the total lengths of the miniaturized 45º and 90º delay lines were reduced to 50% and 25% of the conventional line lengths, respectively. The simulation results are plotted in Fig. 6, and indicate accurate phase shifts and excellent RF performances.

The fabrication processes used are illustrated in Fig. 5. The LC PDL line was fabricated on a 700 μm-thick Borofloat glass substrate (tanα = 3.7 × 10⁻³, attenuation constant = 4.03 × 10⁻⁵ dB/μm) to reduce the substrate losses in the high-frequency band (Fig. 5(a)). A 300 nm silicon nitride (Si₃N₄) layer was deposited by plasma-enhanced chemical vapor deposition as a protective layer (Fig. 5(b)). Because the inductors are located as part of the CPW signal lines, the meander inductors and the CPWs are both of the same thickness and were realized simultaneously by gold electroplating, as shown in Fig. 5(c) and 5(d). Then, a 3 μm polyimide layer, which functions as a sacrificial layer, was spun and patterned to define the anchor area (Fig. 5(e)). Then, a second gold electroplating process was used to form the bridge of the capacitor (Fig. 5(f) and 5(g)). Finally, the air bridge structure was released by removal of the polyimide sacrificial layer with O₂ plasma, as shown in Fig. 5(h).

The compact 45º and 90º LC phase delay units were successfully fabricated using standard MEMS processes, and microscope images of the two units are shown in Fig. 6. The 90º unit consists of two identical components and the total length of the unit is the designed value. The dark regions in Fig. 6 are the overlapped structures, and the holes through the capacitor bridges were opened to accelerate the release of these bridges, and had little effect on the capacitance values.¹⁰ 

The RF performances of the 45º and 90º PDLs were measured using an HP8722ES vector network analyzer. Calibrations were also performed by the on-wafer thru-reflect-line (TRL) method to minimize the effects of the transmission lines.

The measurement results are plotted in Fig. 7. It is shown that the insertion loss (S21), the return loss (S11) and the phase shift (Phase (S21)) are 0.25 dB, 15.82 dB and 44.4º, respectively, at 35 GHz for the 45º delay unit; the corresponding results for the 90º delay unit are 0.62 dB, 15.5 dB and 87.52º, respectively. Across the whole operating band, the phase error is less than 0.6º (1.3%) for the 45º PDL and 2.5º (2.7%) for the 90º case. The validity of the novel compact PDL is demonstrated.

It is also shown in Fig. 7 that the measured performances are consistent with the synthetic simulation results. The insertion loss and the return loss are even better than predicted by the simulations. This means that with only a little modification, the model and the analysis method can be applied to the design of novel compact LC PDLs of any angle, with the necessary size reduction and excellent RF performance.

In this paper, two compact Ka-band LC PDLs based on overlapped meander inductors and air-bridge capacitors have been proposed and fabricated. The transmission line was replaced with the meander inductor and the capacitor was located directly above the inductor, leading to a reduction in the total delay line size. The miniaturized 45º and 90º PDLs were designed based on a semi-lumped model. The electrical and structural parameters in the model were obtained through combined calculations based on transmission line theory and extraction by 3D simulations.

The CPW was impedance-matched to 50 Ω at 35 GHz. The lengths of the 45º and 90º PDLs were 110 μm and 286 μm, respectively, which constitute reductions to 50% and 25% of the lengths of the equivalent conventional transmission lines, respectively. The measurement results are perfectly consistent with the simulation results and confirm the excellent RF performances of the miniaturized structures. From DC up to 35 GHz, the insertion losses of the 45º and 90º delay lines are less than 0.25 dB and 0.62 dB, respectively, and their respective return losses are better than 15.82 dB and 15.5 dB. The corresponding phase delay errors are within 0.6º and 2.5º, respectively. The validity of this novel overlapped structure and the corresponding semi-lumped model have been demonstrated in this paper.

The authors gratefully acknowledge the financial support of the Ministry of Education of China under project no. 2012Z05113.