Experimental demonstration of plasmon–plasmon scattering paves the way for electromagnetic wave-based digital logic concept Open Access

Downscaling, the relentless size reduction approach to enhance the performance of field-effect transistors (FETs), has fueled the phenomenal progress in computing integrated circuit (IC) technology (Moore’s law) for the past 50 years.^1–9 However, the physical device limitations concomitant with extreme downscaling and its prohibitive fabrication cost are great obstacles ushering the demise of such a paradigm.^9–11 Due to the urgent need¹¹ of overcoming the diminishing returns and cost of continuing device downscaling, many “beyond CMOS” devices are being pursued, which exploit various physical phenomena, such as^9,12 (1) particle (electron/hole) charge manipulation (e.g., the Tunneling FET (TFET), the graphene PN junction, and the bilayer pseudo-spin-FET; (2) electron spin manipulation (e.g., the spinFET); (3) magnetic domain wall manipulation (e.g., the spin transfer torque/domain wall device); (4) spin wave manipulation (e.g., the spin wave device); and (5) magnetic coupling manipulation (e.g., nanomagnetic logic and probabilistic spin logic). Many of these device approaches, however, are not amenable to implementation in the established CMOS fabrication infrastructure and, requiring fabrication process modifications, in particular, incorporation of III–V compound semiconductors, graphene, or ferromagnetic or magnetic materials, remain under open-ended development.

While the operation of plasmon–plasmon scattering logic (PPL)^13,14 exploits the biasing of a patterned Metal–Oxide–Semiconductor (MOS) structure into, for example, inversion, similarly to FETs,¹⁵ the similarity stops there; to facilitate its understanding, we present it in three steps. First, we have the MOS structure in Figs. 1(a) and 1(b).¹⁵ Once V_Bias sets the OS interface into inversion and, thus, creates a static electron charge density layer there, a quasi-transverse electromagnetic wave (q-TEM) S_Bias locally disturbs the electron density at the point of impinging into a purposedly chosen long (many micrometers) channel. Due to the long channel, on its own, the charge disturbance would subside in a charge density fluctuation relaxation time; thus, we deemed it to be localized/damped (short-range).¹⁶ However, such a charge disturbance keeps being regenerated continually at the front-end of the q-TEM wave as it propagates toward DO1. We refer to the charge disturbance as a generated localized surface plasma wave (SPW). Because the SPW is generated/transported coincident with the q-TEM’s front-end, its dispersion relation (and speed) is that of the latter. Due to its localized nature, the traditional coherent spatial oscillation of the whole inversion layer charge density does not occur, and there is no necessity to define an SPW oscillation frequency.¹⁷ The continual regeneration of SPWs by the q-TEM wave essentially precludes/avoids their damping^18,19 until DO1 is reached where the combination q-TEM/SPW is detected as a voltage [Fig. 1(a)]. After V_Bias is so large that the electron density in the inversion layer reaches saturation, there are no other possible sources of nonlinearity; the device is linear. Therefore, the input and output waveforms should look similar.

Second, if instead of a straight channel, we pattern the “Y” MOS structure [Fig. 1(c)] and bias it into inversion, the propagating “Bias” q-TEM/SPWs generated by the signal S_Bias would split upon reaching the junction (due to symmetry) and continue to propagate toward DO1 and DO2, where they are detected as substantially equal voltages. In the absence of MOS inversion (or accumulation), i.e., at V_Bias = 0, only the q-TEM wave would be propagating and split at the junction and be detected at DO1 and DO2. The detected voltage in the presence of SPWs would be different than in their absence; this behavior is experimentally demonstrated below.

An antecedent to the PPL device, which embodies the “Y” structure, but with lateral channels (to be explained shortly) converging at the junction, into which no q-TEM waves impinge, is shown in Fig. 1(d). This structure is symmetrical with respect to the junction and behaves similar to that in Fig. 1(c).

Third, the MOS structure in Fig. 1(e), while identical to that in Fig. 1(d), becomes asymmetric when a signal is applied at either S_C1 (with S_C2 = 0) or S_C2 (with S_C1 = 0). In the former case, the repulsive interaction of the q-TEM/SPWs generated by S_C1 and the “Bias” q-TEM/SPWs near the junction causes the latter to be steered toward DO2. For a signal in S_C2 (with S_C1 = 0), the “Bias” q-TEM/SPWs are steered toward DO1. This is the rather timely unorthodox PPL device, whose performance was previously theoretically projected to exhibit femtojoule power dissipations and femtoseconds switching speeds.¹³ PPL represents a departure from cost-prohibitive nanoscale CMOS computing, yet as a universal digital logic gate, it is poised to meet the demanding performance needs of emerging computing systems, such as Central Processing Units (CPUs), graphic CPUs, and Artificial Intelligence Processing Units (AI PUs).^20–22 

Since PPL relies on the interaction of only two q-TEM/SPWs at a time, to demonstrate its key aspects of regenerative transport, repulsive SPW–SPW switching/steering, and detection, it is only necessary to study the partial PPL [Fig. 1(f)]. We briefly present the fundamentals of the partial-PPL device design procedure, which is given in detail elsewhere.¹³ 

We conducted two experiments, measuring an implementation of Fig. 1(d), with θ = 10° and β = 30° (see Fig. 3), and an implementation of Fig. 1(f), with θ = 30° and β = 60° (see Fig. 4). Both cases assumed the set of material properties in Fig. 2. The remaining parameters, namely, the quasi-TEM/SPW waveguide widths, lengths, and junction dimensions, were then determined. Since PPL relies on wave guiding on MOS microstrip lines,²³ techniques to minimize reflection, e.g., impedance matching and waveguide tapering,²⁴ were invoked; the lengths L0, L1, and L2 were chosen much larger than the SPWs’ damping length. Both devices have their aluminum (Al) gate biased by “V_Bias,” which is swept between −30 V and +30 V, including V_Bias = 0. The devices consist of an n-type silicon MOS structure with patterned Al gate over a 400 Å-thick SiO₂ dielectric. Capacitance–voltage measurements on these MOS structures showed that at V_Bias = 0 V, they are neither in inversion nor in accumulation,¹⁵ but that at V_Bias = −10 V and +10 V, they are in inversion and accumulation, respectively. Outside the MOS area, the Al tops a 4300 Å-thick “field” oxide. Measurement results at 294 K and a brief discussion is given below.

Figure 3 shows an implementation of the symmetric structure [Fig. 1(d)] and plots of V_DO1pp and V_DO2pp. At V_Bias = 0 V, the input q-TEM wave (S_Bias) propagates²⁴ yielding output voltages V_DO1pp = 516.3 mV and V_DO2pp = 533.5 mV, i.e., within 3%; this difference is attributed to fabrication-derived asymmetry. When under inversion, the structure yields output voltages V_DO1pp = 713.4 V and V_DO2pp = 737.4 V, also within 3% of each other, but at an average of 39% higher than those at V_Bias = 0 V. These greater output voltages verify that under inversion, there is an extra entity present in addition to the propagating q-TEM wave, accompanying it, that is, what we have described earlier as SPWs, which are responsible for the larger detected voltages at V_Bias = −10 V vs at V_Bias = 0 V.

Figure 4 shows an implementation of the partial PPL [Fig. 1(f)] and plots of V_DO1pp and V_DO2pp. At V_Bias = 0 V, the input q-TEM waves (S_Bias and S_C1) propagate to converge at and emerge from the junction (like in a four-port/-terminal microstrip junction)²⁴ and arrive at DO1 and DO2 yielding output voltages V_DO1pp = 254 mV and V_DO2pp = 249 mV, i.e., within 2%; this is attributed to fabrication-derived asymmetry. For the structure under inversion, the q-TEM waves (S_Bias and S_C1) generate and transport SPWs at their front-end, so the combined q-TEM/SPWs with momenta $k⃗Bias$ and $k⃗C1$ interact (as conceived) repulsively at the junction, yielding the detected voltage V_DO2pp = 320 mV. A voltage V_DO1pp = 226 mV is also detected. This cannot be attributed to fabrication-derived asymmetry, however, since the difference due to asymmetry can only be 2%, whereas the difference between V_DO1pp and V_DO2pp is 41%. This difference must be due to the SPW–SPW repulsive interaction, the effect we sought to demonstrate. Ideally, V_DO1pp should be zero; however, a leakage of the “S_Bias” q-TEM/SPWs into the $k⃗DO1$ direction occurs due to, for example, a difference in arrival time at the junction of the $k⃗Bias$ and $k⃗C1$ q-TEM/SPWs, which allows the “Bias” q-TEM/SPWs to partially escape/miss the repulsive influence from the S_C1 q-TEM/SPWs. The scattering “efficiency” of the process into $k⃗DO2$ may be improved by achieving equal-length microstrip lines S_Bias and S_C1 from the outputs of the Bias-T to the device active area; bending the S_Bias line near the active region by 90° was aimed at doing that [see Figs. 4(b) and 4(c)]. Further optimization may include engineering the shape of the S_Bias and S_C1 waveforms to maximize SPW–SPW interaction time at the junction.

In conclusion, the repulsive interaction of quasi-TEM wave-transported “localized” SPWs at room temperature in the inversion layer of a patterned MOS structure was observed. This fundamental result paves the way for the development of plasmon–plasmon scattering logic (PPL), a revolutionary digital logic concept based on the generation, propagation, and manipulation of plasmons in an electron fluid (EF), which was previously theoretically projected to exhibit femtojoule power dissipations and femtosecond switching speeds, while not demanding expensive nanometer-scale silicon (Si) technology fabrication processes for its implementation.

This work was supported in part by the U. S. National Aeronautics and Space Administration (NASA) under Contract No. 80NSSC19C0476. H.J.D.L.S. thanks the many people who provided their feedback upon critical reading of the manuscript and the anonymous Reviewers whose comments helped improve the paper.

H.J.D.L.S. has Patent 8,509,584 related to this work issued.

H. J. De Los Santos: Conceptualization (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Supervision (equal); Writing – original draft (equal); Writing – review & editing (equal). J. Ge: Methodology (equal); Validation (equal). G. Wang: Data curation (equal); Methodology (equal); Supervision (equal); Writing – review & editing (equal). S. Ding: Data curation (equal); Methodology (equal). P. R. Berger: Methodology (equal); Writing – review & editing (equal). D. R. Gajula: Investigation (equal); Methodology (equal).

The data that support the findings of this study are available within the article.