Comparing post-deposition and post-metallization annealing treatments on Al₂O₃/GaN capacitors for different metal gates

Gallium nitride (GaN) and related materials have attracted the interest of the power electronics community for more than a decade. In particular, lateral devices based on AlGaN/GaN heterojunctions have been extensively explored because of the peculiar high-density and high-mobility two-dimensional electron gas (2DEG).^1–3 However, the lateral topology of GaN-based transistors grown on foreign substrates (e.g., Si, SiC, and sapphire) exhibits some inherent limitations related to the high on-resistance (R_ON), low breakdown (V_BD) and threshold (V_th) voltages, current collapse phenomena at surface states, etc.^4–7 For this reason, at present, an increasing attention is focused on the development of vertical devices based on homoepitaxial GaN-on-GaN,^8,9 due the superior crystal quality and lower dislocation density (<10⁶ cm⁻²) compared with heteroepitaxial GaN.^10–12 

In vertical GaN devices, the breakdown voltage (also exceeding 1 kV) is sustained by tens of micrometers thick drift layers, and the maximum electric field is vertically distributed far from the surface, thus significantly reducing trapping phenomena and dynamic on-resistance effects due to surface states. Moreover, vertical GaN transistors may provide a high positive threshold voltage (V_Th) and high current density, whereas the uniformly distributed electric field and current spread result in better heat dissipation.^13–17 

In this context, the development of vertical GaN power metal oxide semiconductor field effect transistors (MOSFETs) passes through the availability of a good dielectric/GaN interface, characterized by low defect density in order to guarantee a high channel mobility and device reliability. Unfortunately, GaN has no good quality native oxide, and hence, deposited oxides must be adopted. A high dielectric constant (κ), high critical breakdown electric field E_BD, and large band offset to the GaN are the requirements of the ideal gate insulator to effectively limit leakage current and, finally, power dissipation.^18–20 In this context, Al₂O₃ is a particularly promising dielectric due to its relatively high relative permittivity κ (κ = 9), high breakdown electric field (7–8 MV/cm), and suitable conduction band offset to GaN (1.6 eV).^21,22 Atomic layer deposition (ALD), with its nanometric thickness control, uniformity, and conformity, is undoubtedly the ideal technique to grow insulating layers inside the grooved vertical GaN trench-MOSFET¹⁴ and FinFET.²³ However, the as-deposited Al₂O₃ on GaN by ALD is known to suffer from the presence of charges and interface traps, which affect the electrical behavior of metal/Al₂O₃/GaN metal–insulator–semiconductor (MIS) devices in terms of both flat-band voltage (V_FB) shift and stretching of the capacitance–voltage (C–V) characteristics.^21,24–25 To mitigate these issues, various thermal annealing strategies are currently explored at different stages of the MIS device fabrication, either after the ALD deposition¹⁸ [Post-Deposition-Annealing (PDA)] or after the deposition of the metal gate [Post-Metallization-Annealing (PMA)].¹⁹ 

Tadmor et al.²⁶ suggested that the annealing process of Al₂O₃/GaN systems should not exceed 550 °C to avoid the Al₂O₃ degradation as the CV-instability demonstrated. In this perspective, Hashizume et al.^20,27 treated the Al₂O₃/GaN system to a PMA process at 300–400 °C in N₂, demonstrating that such a treatment is beneficial for the electrical performance of the dielectric/GaN system inducing a notable decrease in the interface trap density (D_it). Similarly, Ando et al.²⁸ found that PMA treatments at 400 °C in N₂ are effective to reduce D_it at the Al₂O₃/GaN interface. Moreover, Hung et al.²⁹ found that the reduction in the interface charges by PMA treatments also results in the decreasing gate leakage current. Other studies demonstrated the beneficial effect of PMA treatments to minimize the interface trap states at the Al₂O₃/GaN interface.^25,30,31 However, they only focused on the properties of the Al₂O₃ layer and Al₂O₃/GaN interface, without investigating the possible effects that the PMA approach can have on the metal and on the metal/Al₂O₃ interface of the MIS capacitor.

In this context, it is clear that a unique path toward an ideal Al₂O₃/GaN interface is not yet set. In particular, the comprehension of each single effect that may impact the electrical properties of the Al₂O₃/GaN MIS structure is not yet obtained.

In this article, the direct comparison between PDA and PMA allowed us to highlight the impact of the metal/dielectric interface quality on the behavior of Al₂O₃/GaN MIS capacitors. This aspect is often underrated and only partially addressed. In particular, the comparison among metal gate contacts with different work-functions and electro-affinities [nickel (Ni), molybdenum (Mo), and tantalum (Ta)] enabled us to distinguish the charge-trapping phenomena occurring inside the insulator and at the interface with the semiconductor but also the annealing treatment effect on the metal/dielectric interface as a function of the metal nature.

Vertical MIS capacitors [Fig. 1(a)] have been fabricated on an n-type GaN epitaxial layer (N_D ∼ 2 × 10¹⁶ cm⁻³) grown on 5 μm of conductive GaN bulk substrate (N_D ∼ 10¹⁹ cm⁻³). The epitaxial layer was grown by MOCVD (Metal Organic Chemical Vapor Deposition) in a close-coupled showerhead reactor, using ammonia, trimethylgallium, and hydrogen carrier gas. The x-ray diffraction rocking curves confirmed the lattice matching between the epilayer and the substrate, being the full width at half maximum (FWHM) of the (103) diffraction peak less than 120 arcsec. A Ti/Al/Ni/Au Ohmic contact has been formed on the substrate’s back side using DC magnetron sputtering followed by annealing at 800 °C.³² After the cleaning of the GaN surface in a HF:HCl mixture (essential to remove both native oxide and carbon contaminations), ∼30 nm of Al₂O₃ has been grown by plasma enhanced atomic layer deposition (PE-ALD). Deposition details and process parameters have been already reported in Ref. 22.

According to the schematic flowchart reported in Fig. 1(c), PDA and PMA have been carried out at 400 °C in N₂ for 5 min immediately after Al₂O₃ deposition and metal sputtering, respectively. Different dimensions (side square of 100, 200, 300, and 400 μm) of Ni, Mo, and Ta metal gates [Fig. 1(b)] have been defined by optical photolithography and lift-off. The electrical behavior of the MIS capacitors has been evaluated by capacitance–voltage (C–V) measurements in a CASCADE Microtech probe station, using a Keysight B1505A parameter analyzer.

The C–V curves of the MIS capacitors acquired at a frequency of 1 kHz, before (As-Dep) and after PDA and PMA, are displayed in Fig. 2, for different metal gates: Ni (a), Mo (b), and Ta (c). These graphs report also the theoretical C–V curves calculated by assuming the GaN electron affinity of 4.1 eV, and the commonly reported metal work functions (Φ_Ni = 5.15 eV, Φ_Mo = 4.6 eV, Φ_Ta = 4.25 eV).³³ The values of the metal work function were experimentally verified by the Kelvin-probe force microscopy measurements, reported in the supplementary material (see Fig. S1). All three as-deposited systems exhibit C–V curves characterized by an evident hump between −2 and −1 V, which disappears after either PDA or PMA treatments. Hence, this hump that stretched the C–V curves can be attributed to charge trapping occurring at the Al₂O₃/GaN interface whose quality clearly improves after the application of a thermal budget (regardless of PDA or PMA).^19,20,28,29 This is quantitatively illustrated in Figs. 2(d)–2(f), reporting the energy distribution of the interface trap densities (D_it), calculated by Terman’s method on 1 kHz C–V curves.³³ Interestingly, the distribution of the interface state density exhibits the same behavior independently of the metal gate, and it is characterized by a notable decrease in D_it at about 0.2 eV below the GaN conduction band edge. In fact, D_it decreases from 1 × 10¹³ cm⁻² eV⁻¹ down to 3.5–4 × 10¹² cm⁻² eV⁻¹, with a minimum value of 9–7 × 10¹⁰ cm⁻² eV⁻¹, for all systems after both annealings. These findings are in agreement with previous studies demonstrating that, regardless of the annealing atmosphere, the thermal treatments of oxide/GaN systems are able to improve the interface quality by saturating the Ga-dangling bonds left during the superficial cleaning process of GaN^34,35 and that occurring during the early stage of the ALD growth.³⁶ 

Moreover, paying attention to Figs. 2(a)–2(c), it is possible to observe that both the as-deposited and PDA C–V curves are negatively shifted compared to the theoretical ones. This shift of the flat band voltage V_FB can be justified in different ways. A first and straightforward explanation for the V_FB shift would be entirely due to the presence of positive fixed charges inside Al₂O₃.

It should be noted that if the negative V_FB shift would be only due to positive fixed charges inside the dielectric, an identical V_FB shift should be expected for all three metal gate electrodes, since the Al₂O₃ layer has been deposited under the same conditions and annealed using the same operative parameters, for all three systems. However, as can be seen by Table I, the shifts change as a function of the metal gate electrode. This suggests that besides that the fixed charge inside the dielectric also the charges at the metal/dielectric interface affect the V_FB shift.

In this regard, Yeo et al.³⁷ clearly demonstrated that the work function of a metal gate electrode in contact with a high-k dielectric is not the same vacuum work function, but its value changes from the theoretical ones. In fact, when a metal approaches a dielectric material, it produces the so-called “metal-induced gap states” in the bandgap of the dielectric.³⁸ The charge transfer phenomena at these interfaces create an interfacial dipole that drives the band alignment between the metal and dielectric until a zero-dipole charge position is reached so that the Fermi level E_F of the metal moves toward the charge neutrality level E_CNL of the dielectric (Fermi-level pinning). Therefore, the effective metal work function differs from the vacuum metal work function and, consequently, the experimental V_FB is shifted with respect to the theoretical one.^37–39 

Based on this phenomenon, also our experimental C–V curves, negatively shifted with respect to the theoretical ones, can be explained by the Fermi-level pinning simply occurring for the contact between the metal and dielectric. Moreover, carefully looking at our experimental As-Dep and PDA C–V curves, they overlap from the accumulation to the onset of the above-described hump, beyond which the PDA capacitor appears more positively shifted. The presence of this hump does not actually allow to us evaluate if a real V_FB shift between the As-Dep and PDA devices exists. Instead, the C–V curves of PMA are evidently positively shifted,^19,20 and more importantly, they tend to approach the V_FB of the theoretical curves (V_ThFB). The possible reason is schematically illustrated in Figs. 3(a) and 3(b). As cited above,^37–39 when metal gate electrodes are in contact with high-K dielectrics [Fig. 3(a)], the dipole generated at the interface produces Fermi-level pinning and the effective work functions Φ_Eff,M differ from their vacuum work function Φ_Th,M; thus, the V_FB shift is a direct consequence. As can be observed in Fig. 3(a), all three metal gate electrodes used in this work are characterized by reduced Φ_Eff,M than Φ_Th,M. Moreover, they tend toward a similar energy level value, which should be the E_CNL of the dielectric. However, when PMA processes are carried out, the possible chemical reactions activated at metal/oxide interface can perturb the interfacial dipole, partially or totally removing the Fermi-level pinning phenomena [Fig. 3(b)] and finally restoring the V_FB toward the theoretical value. However, the V_FB shift toward the theoretical value changes as a function of the metal gate electrode (Table I). While for Mo and Ta metal gate electrodes, the PMA treatment is able to almost totally restore the theoretical V_FB, for Ni, it occurs only partially [Fig. 2(a)]. This different behavior can be correlated with the different nature of the metal gate electrode. In this regard, it has been demonstrated that metals characterized by high work function do not easily react with oxygen.⁴⁰ This suggests that Ni, characterized by higher work function than Mo and Ta, poorly react with the underlying oxide layer during the annealing process, producing a less effective perturbation of the dipole and finally of the V_FB shift.

The possible impact of longer PMA treatments (5 + 20 min) on the V_FB shift has been also investigated for all three systems, and the corresponding C–V curves are shown in Figs. 4(a)–4(c). Interestingly, for all three metals, the C–V curves remain almost unchanged in terms of V_FB, independent of the annealing time (5 min or 5 + 20 min).

On the other hand, the PMA duration strongly impacts the hysteresis value of C–V curves acquired considering forward and backward sweep. As clearly reported in Fig. 4(d), the As-Dep capacitors exhibit a significant hysteresis around 3 V because of the charge-trapping phenomena by the electrically active defects inside the high-κ and at the interface, generally known as oxide-charge traps.^41,42 PDA and PMA approaches are similarly beneficial to reduce the hysteresis phenomena toward a value of about 2 V. This means that, regardless of the procedure, the annealing process is useful to suppress oxide-charge traps and finally to mitigate the charge trapping phenomena. Moreover, increasing the PMA period up to 20 min, the hysteresis value is further reduced by about 1 V for all metal gate electrodes. Hence, considering that the C–V hysteresis is ascribable to the quality of the entire dielectric layer, it cannot be ruled out that a further increase in the annealing time may lead to an additional reduction of the trapping phenomena.

In conclusion, in order to understand the impact of the metal/dielectric interface quality on the behavior of the Al₂O₃/GaN MIS capacitors, two different annealing approaches have been investigated: PDA and PMA, i.e., annealing on the bare Al₂O₃ layer and annealing after the gate metallization deposition on Al₂O₃. Both PDA and PMA showed similar improvements of the Al₂O₃/GaN interface quality, by reducing the D_it values, and they also improved the dielectric quality, decreasing the hysteresis. However, differently from PDA, the PMA treatment gives an additional beneficial effect on the metal/dielectric interface. In fact, PMA approaches have been found to be able to stabilize V_FB, shifting this toward the theoretical value. We attribute this beneficial effect to the possible chemical reactions activated by the annealing process at the metal/dielectric interface, which can perturb the known metal/dielectric dipole responsible for Fermi-level pinning phenomena and consequently the V_FB shift than the theoretical value. However, the response to PMA treatment is a function of the used metal gate. In this regard, we found that the Ni metal gate, characterized by higher work function than Mo and Ta, does not reach the theoretical V_FB even after 5 + 20 min long PMA treatment. This could be due to its lower tendency to react with the underlying oxide during the annealing process.