This paper reports on the extraction of the equivalent circuit model parameters of a physically defined silicon quantum dot at a cryogenic temperature and design of the impedance matching circuits to improve the performance of a charge sensor for radio-frequency (RF) reflectometry. The I-V characteristics and the S-parameters of the quantum dot device are measured around a Coulomb peak at 4.2 K. The measured results are modeled by an RC parallel circuit, and the model parameters for the quantum dot device were obtained. We consider three impedance matching circuits for RF reflectometry of a quantum dot: shunt capacitor-series inductor type, shunt inductor-series capacitor type, and shunt inductor-series inductor-type. We formulate and compare the sensitivity and bandwidth of RF reflectometry for the three types of circuits. The analysis should be useful for selecting the optimal matching circuit and the circuit parameters for given equivalent circuit parameters and working frequency. This procedure is demonstrated for a quantum dot with the characterized model circuit along with simulated performance. This design technique of matching circuit for RF reflectometry can be applied to any device that can be represented by an RC parallel circuit. These results will facilitate to realize fast semiconductor qubit readout in various quantum dot platforms.

## I. INTRODUCTION

Radio-frequency (RF) reflectometry on a semiconductor quantum dot (QD) charge sensor^{1–3} has high sensitivity to changes in nearby electric fields and is useful for spin qubit readout.^{4–25} A typical QD charge sensor becomes most sensitive at a resistance of ∼1 MΩ, and it is generally understood that realizing a good impedance matching of this sensor resistance to the 50 Ω circuit is a key to achieve high reflectometry sensitivity. Therefore, it is important to design the impedance matching circuit based on the effective circuit model of the QD charge sensor. However, the QD charge sensor is located in a cryogenic environment where precise calibration of the high-frequency transmission properties is challenging, making detailed evaluations of the QD to extract the equivalent circuit parameters elusive. Furthermore, there are several types of circuits proposed or utilized for the purpose of RF reflectometry measurements of a QD charge sensor, which necessitates design methodology and trade-off analysis between the sensitivity and the bandwidth for different circuits.

In this paper, a physically defined silicon QD^{26–28} is fabricated and characterized as a testbed to establish the design scheme of a matching circuit for RF reflectometry. The I-V characteristics and S-parameters of the QD are measured to extract the equivalent circuit parameters at the measurement plane located on the bonding pads of the QD chip. The expected sensitivity and bandwidth are analytically obtained for three simple, typical kinds of matching circuits. The result can be used to obtain the optimal circuit parameters given the model parameters for the QD sensor and the target performance. The circuit design formulations are derived to obtain impedance matching between the 50 Ω input port and the QD equivalent circuit represented by an RC parallel circuit. The sensitivity to changes in the resistance or capacitance and the frequency bandwidth are analyzed and compared among the circuits. A selection criterion for the appropriate circuit in terms of sensitivity and bandwidth is given, and its simulated performance for the quantum dot measured in the experiment is presented.

## II. DEVICE

The device used in this study is an n-type physically defined silicon QD fabricated as previously reported.^{27,28} Figure 1(a) shows a scanning electron microscope image of the physically defined silicon QD device. The device has an n+-polysilicon top-gate on top of an insulating layer that induces electrons in the silicon-on-insulator (SOI) layer. The sensor QD is connected to the source and drain electrodes, and one side-gate located nearby is biased to adjust the potential of the sensor QD. The drain and source contacts of the charge sensor QD are connected to ports one and two of the vector network analyzer (VNA) via RF-through of bias tees, respectively, as well as to DC measurement systems via DC-through of bias tees. Figure 1(b) shows a photograph of the silicon QD chip mounted on a printed circuit board (PCB). Each pad on the silicon chip is connected to the external circuitry by bonding wires and transmission lines. Sub Miniature Type A (SMA) connectors are mounted on the back side of the PCB and connected to the measurement system via RF cables. The calibration planes of the S-parameter measurement are at the SMA connectors on the PCB, and the S-parameters between the source and drain bond pads are obtained by a de-embedding technique from the measurement results of calibrated S-parameters and the simulated S-parameters between the pads and the SMA connectors on the PCB (S-parameters of the PCB and connectors are simulated with Ansys HFSS, bonding wires simulated with Keysight ADS).

## III. MEASUREMENTS

A detailed equivalent circuit of a QD can be given by using a parasitic capacitance, a tunnel junction (consisting of a parallel circuit of tunnel resistance and tunnel capacitance), and a gate-voltage dependent current source.^{29} While this can reproduce various electrical properties (including IV characteristics), for RF reflectometry, it can be simplified to a good approximation as a parallel circuit with only a resistor and a capacitor.^{4} Theoretically, both of these parameters can be evaluated only by measuring the S-parameters. The reflection coefficient should ideally yield both the resistance (*R*_{QD}) and the capacitance (*C*_{QD}) of the QD. *R*_{QD} can be calculated from the reflection coefficient at low frequency. When the absolute value of reflection coefficient at low frequencies, such as near DC, is Γ_{0} and the port impedance is *Z*_{0}, *R*_{QD} is calculated as

The capacitance of the QD (*C*_{QD}) is calculated as

where Γ is the absolute value of the reflection coefficient, *θ* is the reflection phase, and *ω* is the angular frequency. However, *R*_{QD} is difficult to extract accurately only from the reflection amplitude since it is very high compared to *Z*_{0} = 50 Ω. Therefore, in this paper, we calculate the resistance from the I-V characteristic.

Figure 2 shows the I-V characteristic and S-parameters of the QD device. All measurements were performed at a temperature of 4.2 K, for a top-gate voltage of 10 V, and a drain voltage of 300 *µ*V. The I-V characteristic is measured using a lock-in amplifier technique at 71 Hz. I-V amplifier and AC voltmeter are used and the current values are calculated from their conversion factors. Figure 2(a) shows the side-gate voltage (*V*_{sg}) dependence of the drain current (*I*_{ds}). The current shows a peak when the side-gate voltage is swept between −2.5 and −4.0 V: a so-called Coulomb peak^{30} of the QD. Figure 2(b) shows the *V*_{sg} dependence of the resistance of the charge sensor QD (*R*_{QD}). Figure 2(c) compares the phase of S_{11} for *V*_{sg} = −3.5 and −4.0 V, for which the change in conductance is large. We note that RF reflectometry can read out the change in the resistance and/or the capacitance of a QD due to the variation in the QD potential or the energy dispersion. However, the *V*_{sg} dependence of the reflection phase of the QD is found small enough to be neglected in this device, meaning that the reflection phase in the present circuit is not sensitive to the resistance change. Its frequency dependence can be well fit by the RC model circuit with *R*_{QD} = 1.4 MΩ and *C*_{QD} = 65 fF using Eq. (2), suggesting the validity of the model in this frequency range. The value of the resistance of the QD is higher than that of typical gate defined Si/SiGe QD^{31} (∼100 kΩ) because we use physically defined QD. Physically defined QD can be realized with fewer gates compared to gate defined QDs, but it is difficult to adjust tunneling resistance electrically. The value of *C*_{QD} is smaller than the typical parasitic capacitance (on the order of several hundreds of fF) seen in the conventional reflectometry measurements with bond wires or transmission lines of PCBs included.^{5}

## IV. CIRCUIT DESIGN AND ANALYSIS

The circuit model obtained above should help to devise the matching circuit toward improved sensing performance. In the following, three simple impedance matching circuits are considered as schematically shown in Fig. 3 and a comparison is given in terms of sensitivity and impedance matching bandwidth. In all types (a, b, and c), the matching circuit consists of two elements, one series and one shunt. The charge sensor QD is modeled by an RC parallel circuit, parameterized by *R*_{QD} and *C*_{QD} that take the values of *R*_{0} and *C*_{0}, respectively, under the default bias condition. The values of the components in the matching circuit for a given working (angular) frequency *ω* = *ω*_{0} are then determined to match the input impedance of the overall circuits (*Z*_{x} with *x* = a, b, c) to the port impedance (*Z*_{0}). The sensitivity indices to a change in *R*_{QD} (*S*_{R}) and to a change in *C*_{QD} (*S*_{C}) for circuit *x* are defined as

respectively. The larger the absolute value of the index, the higher the sensitivity to the corresponding change. In addition, the frequency derivative of the impedance

can be used to evaluate the bandwidth of impedance matching at the default bias. The smaller the absolute value of this value, the wider the bandwidth of impedance matching. Table I shows the calculation results for the three matching circuits. Note that in the calculation, *R*_{0} > *Z*_{0} is assumed. The circuit parameters in Table I give the values for which the impedance matching to *Z*_{0} is realized. The calculated values of the circuit parameters for circuits (a), (b), and (c) are shown by Eqs. , , , , , and , respectively. Interestingly, the resistance sensitivity indices, |*S*_{Ra}|, |*S*_{Rb}|, and |*S*_{Rc}|, are the same values for the three circuit types, as given by Eqs. , , and . These expressions show that higher sensitivity to change in resistance of QD is obtained by lowering *R*_{0} (closer to *Z*_{0}). The capacitance sensitivity indices, |*S*_{Ca}|, |*S*_{Cb}|, and |*S*_{Cc}|, are also the same for three circuits, as shown by Eqs. , , and . Based on the calculation, the capacitance sensitivity will be enhanced by increasing *R*_{0} and *ω*_{0}. We note that the sensitivity will be improved for a smaller value of *R*_{0} for resistance readout while the opposite is the case for capacitance readout, meaning that the optimal condition depends on the readout mode. The bandwidth indices, |*D*_{ωa}|, |*D*_{ωb}|, and |*D*_{ωc}|, are shown by Eqs. , , and . It can be seen that the frequency bandwidths are wider in the order of circuits (c), (a), and (b). Based on the discussion up to this point, it may seem that circuit (c) is the best among the three, with the widest bandwidth |*D*_{ωx}| and the identical sensitivities (|*S*_{Rx}|, |*S*_{Cx}|). However, this circuit cannot be always used, since for a particular combination of the values of *R*_{0} and *C*_{0}, the shunt inductance value given by Eq. becomes negative [see also expression ]. In this parameter regime, circuit (a) becomes realizable and will be the best choice among the three. The diagram of the best circuit as a function of *R*_{0} and *C*_{0} is given in Fig. 4 for several different values of the working frequency, *ω*_{0}/(2π). In the lower left region of the line, circuit (a) can be realized, and in the upper right region, circuit (c) can be realized. On the lines, a matching circuit with only one series inductor can be realized. The boundary is at 293 MHz for the extracted RC parameters. Once the equivalent circuit parameters are known, the optimal circuit configuration can be determined accordingly.

. | Circuit (a) . | Circuit (b) . | Circuit (c) . |
---|---|---|---|

Circuit parameters | $Ca=1\omega 0R0R0\u2212Z0Z0\u2212C0(6)$ | $Cb=1\omega 0R0\u2212Z0Z0(12)$ | $Lc1=R0Z0\omega 0\omega 0C0R0Z0\u2212R0\u2212Z0Z0\u2212C0(17)$ |

$La=R0\u2212Z0Z0\omega 0(7)$ | $Lb=R0Z0\omega 0\omega 0C0R0Z0+R0\u2212Z0Z0(13)$ | $Lc2=R0\u2212Z0Z0\omega 0(18)$ | |

|S_{Rx}| | $Z0R0\u22122Z0R02(8)$ | $Z0R0\u22122Z0R02(14)$ | $Z0R0\u22122Z0R02(19)$ |

|S_{Cx}| | $2\omega 0Z0R0\u2212Z0Z0(9)$ | $2\omega 0Z0R0\u2212Z0Z0(15)$ | $2\omega 0Z0R0\u2212Z0Z0(20)$ |

|D_{ωx}| | $2(R0\u2212Z0)Z0\omega 0R0(10)$ | $2(R0\u2212Z0)Z0\omega 0R0+4C0Z0R0\u2212Z0Z0(16)$ | $2(R0\u2212Z0)Z0\omega 0R0\u22124C0Z0R0\u2212Z0Z0(21)$ |

Restrictions | $\omega 0<1C0R0R0\u2212Z0Z0(11)$ | ⋯ | $\omega 0>1C0R0R0\u2212Z0Z0(22)$ |

. | Circuit (a) . | Circuit (b) . | Circuit (c) . |
---|---|---|---|

Circuit parameters | $Ca=1\omega 0R0R0\u2212Z0Z0\u2212C0(6)$ | $Cb=1\omega 0R0\u2212Z0Z0(12)$ | $Lc1=R0Z0\omega 0\omega 0C0R0Z0\u2212R0\u2212Z0Z0\u2212C0(17)$ |

$La=R0\u2212Z0Z0\omega 0(7)$ | $Lb=R0Z0\omega 0\omega 0C0R0Z0+R0\u2212Z0Z0(13)$ | $Lc2=R0\u2212Z0Z0\omega 0(18)$ | |

|S_{Rx}| | $Z0R0\u22122Z0R02(8)$ | $Z0R0\u22122Z0R02(14)$ | $Z0R0\u22122Z0R02(19)$ |

|S_{Cx}| | $2\omega 0Z0R0\u2212Z0Z0(9)$ | $2\omega 0Z0R0\u2212Z0Z0(15)$ | $2\omega 0Z0R0\u2212Z0Z0(20)$ |

|D_{ωx}| | $2(R0\u2212Z0)Z0\omega 0R0(10)$ | $2(R0\u2212Z0)Z0\omega 0R0+4C0Z0R0\u2212Z0Z0(16)$ | $2(R0\u2212Z0)Z0\omega 0R0\u22124C0Z0R0\u2212Z0Z0(21)$ |

Restrictions | $\omega 0<1C0R0R0\u2212Z0Z0(11)$ | ⋯ | $\omega 0>1C0R0R0\u2212Z0Z0(22)$ |

Based on the analysis above, an optimal impedance matching circuit can be designed for our QD using the extracted equivalent circuit parameters (*R*_{0} = 1.4 MΩ and *C*_{0} = 65 fF, that is, the default bias is *V*_{sg} = −3.5 V). The port impedance of the reflection measurement is assumed to be 50 Ω, which is the standard for normal measurement systems. The working frequency is assumed to be 2 GHz—we note that a higher frequency leads to wider matching bandwidth [see , , and ] and compact circuit parameters but it comes at the cost of the increased effects of parasitic components. Figure 4 indicates that for the given parameters, circuit (c) should be optimal in terms of the bandwidth with the resistance sensitivity equivalent to that from circuit (b) while circuit (a) cannot realize impedance matching. Using expressions ) and , the circuit parameters are calculated as *L*_{c1} = 114 nH and *L*_{c2} = 666 nH. The performance of the designed circuit is checked by small-signal simulation (see Fig. 5). The reflection is calculated for different values of *V*_{sg} or *R*_{QD}, which emulates the effect of the electric field change at the sensor QD. Figure 5(a) shows the frequency dependence of the reflection amplitude of the designed QD charge sensor for two conditions: *R*_{QD} = 1.4 MΩ and *C*_{QD} = 65 fF corresponding to *V*_{sg} = −3.5 V (the red solid trace) and *R*_{QD} = 5.1 MΩ and *C*_{QD} = 65 fF corresponding to *V*_{sg} = −4.0 V (the blue dashed trace). When *V*_{sg} is changed from *V*_{sg} = −3.5 V to −4.0 V, the reflection amplitude at 2 GHz changes from less than −40 dB to about −4.9 dB (due to design accuracy and measurement accuracy, there is no predominant difference below −40 dB). The bandwidth with reflection amplitude of less than −10 dB is 0.8 MHz, which is sufficient for high-speed readout and multiplexing. Figure 5(b) shows the *R*_{QD} dependence of the reflection amplitude at 2 GHz. The reflection amplitude is changed significantly when the value of *R*_{QD} is varied from *R*_{QD} = 1.4 MΩ, where the circuit is impedance matched to the 50 Ω system.

## V. CONCLUSION

In conclusion, a physically defined silicon QD device was measured, and the equivalent circuit parameters of the QD chip at a cryogenic temperature were extracted from the S-parameter measurements in combination with the deembedding technique. Design methodology for the three matching circuits consisting of two LC components was established, with comparisons made in terms of the sensing sensitivity and bandwidth. The design and the simulation of the impedance matching circuit with a series inductor and a shunt inductor are performed. A concrete design procedure is outlined once the equivalent circuit parameters for the QD chip are obtained. These results should facilitate the realization of RF reflectometry of semiconductor qubits on various QD platforms.

## AUTHOR DECLARATIONS

### Conflict of Interest

The authors have no conflicts to disclose.

### Author Contributions

**J. Kamioka**: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal). **R. Matsuda**: Data curation (supporting); Writing – review & editing (supporting). **R. Mizokuchi**: Writing – review & editing (supporting). **J. Yoneda**: Supervision (supporting); Writing – review & editing (equal). **T. Kodera**: Project administration (lead); Resources (lead); Supervision (lead); Writing – review & editing (equal).

## DATA AVAILABILITY

The data that support the findings of this study are available from the corresponding author upon reasonable request.