MN-ADC based on high-reliable 2T2R synapse structure Open Access

A neuromorphic computing system based on a memristor is an energy-efficient approach for various applications in information processing, such as handwriting recognition,¹ speech recognition,² and path planning.³ Traditional analog-to-digital converters (ADCs) have the dilemma of the trade-off among the sampling speed, power consumption, and conversion accuracy.⁴ However, the memristor-based neuromorphic ADC (MN-ADC) combines the advantage of neuromorphic computing⁵ and artificial intelligent learning algorithms,⁶ which, therefore, possesses the ability to break through the bottleneck and improve the performance of the ADC.⁷ 

To maintain the dynamic performance of MN-ADCs, the conductance of the memristors that act as the synapses of neural networks needs to be precisely tuned. In Ref. 8, the conductance of the memristors in the 1T1R array is offline tuned to overcome the nonlinearity in the static I–V transformation; however, this approach does not take into account the variation of the nonlinearity. In Refs. 7 and 9, the authors add the reversed conduction circuit and build the synaptic unit based on 2T1R devices to support online training with a pre-designed training dataset. However, when neuromorphic computing is implemented in practical circuits,¹⁰ the temporal relationship (Δt) of activity between neurons before and after synapses becomes a determinant of long-term plasticity.¹¹ This will result in that the conductance of the memristors cannot be stably read and written in high-speed real-time applications; thus, the bandwidth of MN-ADC will be limited by the performance of memristive synapses.¹² Moreover, an indirect type of memristor-based A/D converter is proposed in Ref. 13, where the input analog voltage is converted into the counting value. The design is analyzed and simulated to prove its anti-interference ability for zero-mean noise. And Ref. 14 takes a novel systematic approach to design the memristive data converter that is capable of reconfigurable quantization and logarithmic encoding, which can dramatically reduce data dimensions. These designs are the indicative of the growing importance of memristive ADCs.

In this paper, we present the design of an MN-ADC with a 2T2R synaptic unit,¹⁵ which can overcome the undesired effects of resistance variation and spike-timing-dependent-plasticity (STDP) learning rules¹⁶ and, thus, improve the conversion accuracy and the sampling speed. First, we measured the resistance states and retention properties of the device on the fabricated 1 K RRAM array. The STDP behavior of the synapses is also tested. To handle these non-idealities, an MN-ADC with a 2T2R synaptic unit is proposed, and we also give the circuit design with a standalone 1T1R array. Simulation results evaluate the performance of the MN-ADC and demonstrate that the synapses composed of 2T2R unit can reduce noise and avoid the large resistance variation under the condition of high-frequency regulation.

This paper is arranged as follows: Sec. II gives the motivation. Section III presents the design of MN-ADC. Section IV verifies the design with simulation and comparison. Section V concludes this paper.

For traditional ADCs, many imperfections of analog CMOS circuits will degrade the dynamic performance, such as the mismatches of the resistor/capacitor network and the bias offset of op amps and comparators.¹⁷ Similarly, the non-ideal properties of memristor array¹⁸ will greatly limit the performance of MN-ADC. Figure 1(a) shows the measured resistance states in a fabricated 1 KB memristor array.¹⁹ The stack structure of the memristor array is TiN/TaOx/HfOx/TiN, the front-end fabrication is completed in a commercial CMOS foundry, and the drain side of the transistor is carried out in-house. Although the resistance states of the device do not decay significantly for more than 10 hours, the fluctuation ranges of different resistance levels are not consistent, which will limit the conversion performance.²⁰ The overall retention properties are quantitatively summarized in Fig. 1(b). To maintain the dynamic performance of the MN-ADC, the analog circuits should cope with the fluctuation of the synapses.

When handling with the fluctuation of the synapses, MN-ADC should avoid interrupting the normal conversion process. It means that both the sampling and online training (i.e., conductance tuning) should be arranged to operate alternatively. Otherwise, the training process will limit the overall sampling speed. Furthermore, according to the STDP rules shown in Fig. 2, the conductance (weight) change in the synapses is inversely related to the time interval between two regulating pulses (denoted as Δt). Here, we define the change in conductance as

where W_res and W_ini are the resulting conductance after adjustment and the initial conductance, respectively. As illustrated in Fig. 2, Δ_G increases along with |Δt| decreases. When Δt > 0, the conductance of the synapse will increase, and Δ_G will decrease with the increase of Δt. Conversely, when Δt < 0, the conductance decreases, and Δ_G increases as the absolute values of Δt increase. Therefore, it is found that the change in conductance (Δ_G) is directly proportional to the learning rate η = Δ_R/R of the STDP rules,⁷ where Δ_R is the change in resistance. Consequently, to accurately adjust the conductance, one needs to effectively modulate the inter-pulse interval Δt. Considering the above two issues, we need to design the synaptic unit in a way that balances conversion speed and adjustment accuracy.

Figure 3 shows the proposed 4-bit MN-ADC with an adjustable 2T2R synaptic unit. The circuit mainly consists of a 2T2R synaptic unit realized in a 1T1R array, and the peripheral neurons (op amps) and MUX. The top electrode WL of the 1T1R was connected to the input of the artificial neuron g_i, whereas the bottom electrode BL was injected with the feedback signal S_i. As shown in Fig. 4, one CLK cycle is divided into two parts, the conversion period (C) and the adjustment period (A). During the adjustment period, the feedback signals S_i are switched to the tuning signals u_i. For the conversion period, MN-ADC converts the analog input V_IN into digital outputs D_i, and the feedback signal S_i switches to D_i. It is noted that the gate signals e and u_i are generated by the external control circuit according to Ref. 11. As seen in Fig. 4, the MN-ADC is first in the steady state, where it always accepts the feedback signal D_i. When entering the unsteady state due to the resistance variation, the MN-ADC switches between the conversion period and the adjustment period. Finally, with the adjustment of conductance, the MN-ADC regains the desired dynamic performance and enters the next steady state.

In the conversion period, the circuit model of the MN-ADC in Fig. 3 can be represented as

where V_ref is the full-scale reference voltage, V_IN is the analog input, W denotes the conductance of the synaptic unit, and D_i is the digital output. And g is the activation function defined as

The activation function g(x) corresponds to the neuron g_i, which is realized by the op amps. Through the multiplication and addition relationship of the circuit, the MN-ADC completes the conversion period.

In practical applications, the ability to suppress the circuit’s noise needs to be given special consideration.^13,14,21 Therefore, we further analyze the noise reduction performance with the proposed 2T2R synaptic units and give the corresponding derivations. As shown in Figs. 3 and 4, in the conversion period, the noise of W_ij includes the fluctuation of memristor resistance, and thermal and flicker noise of the transistors. Without loss of generality, we can represent the noise of two 1T1R cells of one 2T2R unit as two independent sources of thermal noise,²² where the power spectral density of current noise is denoted as $Inl2̄=4kTG1$ and $In22̄=4kTG2$⁠. Here, k is the Boltzmann constant, T is the temperature, and G₁ and G₂ are the equivalent conductance for each 1T1R cell in Fig. 5. Since the two noise sources of 2T2R are uncorrelated, the total power $In,s2̄$ of the 2T2R synaptic unit can be defined as

Therefore, the equivalent voltage noise is calculated as

Since G₁ is approximately equal to G₂ after weight adjustment in the steady state, the equivalent voltage noise applied to the amplifier is half of the noise value, as presented in Ref. 7 using the 1T1R synaptic unit. This will be further demonstrated in the simulations of Sec. IV, where a 6 dB improvement of SNDR has been achieved by using the 2T2R synaptic unit compared with the design in Ref. 7.

In the adjustment period, we should match the memristive neural network by precisely tuning W_i and W_ij. In this paper, the stochastic gradient descent (SGD) algorithm⁷ is utilized to iterate the weights

where η is the learning rate and E_sgd is the loss function. For each iteration, the weight ΔW_i,j(n + 1) is updated on the basis of the gradient of $∇Wi,jEsgd(n)$⁠. The supervised learning scheme is trained and tested with the ideal analog/digital datasets of (V_IN, T_i), where T_i represents the correct target results for each analog input pattern V_IN. The loss function E_sgd is defined as

According to Ref. 11, ΔW_i,j is translated into the tuning signals u_i, which is based on the parameters in Fig. 2.

In this section, we evaluated the proposed MN-ADC and compared its performance with the design presented in Ref. 7. A single sinusoidal with the frequency of 4.4 kHz is adopted as the input signal. The sampling rate is set as 50 kHz. The non-ideal properties of the memristive synapses are based on the measured data in Fig. 1. As shown in Fig. 6(a), we compare the mean value of E_sgd in (7), which represents the convergence accuracy of the memristive neural network,

where L is the number of samples in a single signal period. In Fig. 6(a), we first include the resistance variation presented in Fig. 1. It is seen that, compared with the design in Ref. 7, the proposed MN-ADC can achieve a smaller convergence error, which equals a higher effective conversion resolution. Such performance could be attributed to the 2T2R synapses, which reduce the noise originated from the resistance variation by a factor of 2. After the integration and activation of the neuron [as the function of g(x)], the error will be proportional to the slew rate of the amplifier. Therefore, the activation function nonlinearly amplifies the signal along with the noise caused by the resistance variation. The mean error $Ẽsgd$ of the proposed MN-ADC reaches around 0.001, which is a 20-fold improvement compared with the design in Ref. 7.

Furthermore, we take into account the effects of Δt of STDP rules. Recall that from Sec. II, the conductance change in the synapses is inversely related to the time interval between two regulating pulses (denoted as Δt). With the same sampling rate, due to the use of a 2T2R synaptic unit, the memristor receives regulating pulses with an interval of 2Δt, whereas it is Δt for the MN-ADC in Ref. 7. Consequently, the achieved Δ_G will be smaller, which produces better convergence accuracy as depicted in Fig. 6(b).

Finally, the dynamic performance of the MN-ADCs is evaluated. We use the histogram method to measure the non-linear parameters of the MN-ADCs. For the MN-ADC in Ref. 7, Figs. 7(a1)–7(a3) show the performance of integral nonlinearity (INL), differential nonlinearity (DNL), and the frequency spectrum, respectively. It is seen that the INL error is 0/−1.49 LSB, the DNL is +0.23/−0.68 LSB, and the effective number of bits (ENOB) only reaches 2.74 bit for a 4-bit MN-ADC. For the proposed MN-ADC based on a 2T2R synaptic unit, the iterative training process becomes more stable and accurate, and the dynamic performance benefits from this. According to the results of Figs. 7(b1)–7(b3), the INL and DNL are decreased to 0/−0.16 LSB and 0.02/−0.07 LSB, respectively. Moreover, the ENOB can be optimized to 3.77 bit, which is 1 bit higher than the design in Ref. 7.

To further evaluate the conversion capability of the MN-ADC, we adopt a two-tone sinusoidal input signal with the frequencies of 4.4 and 6.6 kHz. As illustrated in Fig. 8, the output frequency spectrum, except for the signal components, spurs are suppressed near the noise floor. And the SFDR, therefore, reaches 34.66 dB, which is equivalent to the dynamic performance with a single input sinusoidal.

In this paper, we propose an MN-ADC with a 2T2R synaptic unit. The proposed neural synapse can be fully realized in the 1T1R array. Compared with the previous work, our design considers the influence of resistance variation and STDP learning rules under the condition of high-speed regulation. Simulation results demonstrate the performance of the proposed MN-ADC. It is noted that using this 4bit MN-ADC as a base unit, one can construct pipeline ADCs with higher resolution.

Weihe Wang and Yinan Wang contribute equally to this work. This work was supported by the National Natural Science Foundation of China (Grant Nos. 61974164, 62074166, 62004219, 62004220, and 62104256), the National Key Research and Development Plan of MOST of China (Grant No. 2019YFB 2205100), and the Science Support Program of National University of Defense and Technology under Grant No. ZK20-06.

The authors have no conflicts to disclose.

Weihe Wang: Conceptualization (equal); Data curation (equal). Yinan Wang: Data curation (equal); Formal analysis (equal). Zhiwei Li: Funding acquisition (equal). Xingzhi Fu: Funding acquisition (equal). Mingxin Deng: Methodology (supporting). Xiaojuan Liu: Project administration (equal). Qingjiang Li: Methodology (equal). Hui Xu: Funding acquisition (supporting).

The data that support the findings of this study are available from the corresponding author upon reasonable request.