Analytical drain current and performance evaluation for inversion type InGaAs gate-all-around MOSFET

Electrostatic control in three dimensions has become imperative to reduce the short channel effects (SCEs) in deeply scaled transistors beyond the 22 nm technology node. The gate-all-around (GAA) MOSFET has proven to provide the greatest immunity to SCEs with the shortest natural length (λ) and impose stronger gate control over surface carriers.^1–3 Tremendous effort expended behind silicon nanowires and the incorporation of strain engineering reveal the potential of silicon as a favorable channel material for CMOS technology.^4–6 However, phonon scattering and surface roughness from the wrap-around gate configuration limit the mobility to subpar levels, impeding the performance of silicon nanowires from reaching near ballistic limits. This opens room for further improvement in carrier transport by utilizing high mobility III–V semiconductor channel materials.

To this end, InGaAs has attracted the attention of researchers as a viable candidate for providing superior drain current in both on and off states.^7–9 On one hand, intense research in the past four decades has ushered significant progress on the use of atomic layer deposition (ALD) to integrate a thermodynamically stable high-κ dielectric on a III–V semiconductor, which drastically reduces gate leakage current of InGaAs based transistors, offering better effective oxide thickness (EOT) for minimization of static power dissipation.¹⁰ On the other hand, the inherent high mobility of a III–V semiconductor as the active channel material truncates dynamic power dissipation in the transistor, offering the same drive current at a reduced supply voltage.¹¹ This favored InGaAs gate-all-around MOSFETs to gain popularity in switching and logic applications.⁹ 

Although both cylindrical nanowires and rectangular GAA MOSFETs have exhibited excellent transport and subthreshold performance recently,^12,13 the rectangular geometry offers an additional advantage in terms of the fabrication viewpoint. First, the seamless integration of rectangular MOSFETs with FinFET technology is possible because lateral nanowires bear strong resemblance with the FinFET architecture. This minimal deviation in the fabrication process encourages the semiconductor industry to reap the benefits provided by rectangular GAA MOSFETs over its cylindrical counterparts. Moreover, rectangular GAA MOSFETs can be grown epitaxially into thin nanosheets unlike cylindrical nanowire MOSFETs, which are grown by the vapor–liquid–solid (VLS) method.¹⁴ This enables precise control of nanowire height in the rectangular geometry. One of the challenges in fabricating cylindrical nanowire is controlling the shape of the nanowire since the transport properties rely heavily on the nanowire diameter.¹⁵ This difficulty is circumvented in rectangular GAA MOSFETs with etching techniques, allowing exact control of nanosheet width. Monolithic 3D stacking has persuaded researchers to explore the prospect of stacked nanosheets with a goal to achieve higher current drive while ensuring more W_eff under the same footprint as FinFETs.^16,17

There have been numerous experimental reports on InGaAs MOSFETs exhibiting high drain current and excellent subthreshold characteristics.^3,7,8,18 Recently, short channel InGaAs GAA nanowire has been studied via top down approach, and numerical simulation of such a device illustrated volume inversion inside the active region for a fin width as low as 30 nm, which otherwise would require deca-nanometer dimensions for silicon counterparts.^19,20 Quantum mechanical simulations were carried out by Khan et al. to determine electrostatic charge and carrier transport under the uncoupled mode space approach, which is computationally expensive and often depends on the numerical convergence of the solution.^21,22 Existing analytical models developed for double-gate MOSFETs cannot be extrapolated to GAA geometry without involving proper physics into the Poisson equation. Compact models developed for silicon nanowires use a constant difference in potential between the center and the surface, which results in deviations near the threshold region and cannot be applied to the strong inversion operation.²³ Moreover, in InGaAs MOSFETs, a saturation of the decrease in subthreshold current is observed due to high drain junction leakage, which is not reflected by silicon based analytic reports.¹¹ Besides, fixed oxide charge and interface trap defects are neglected in these models, which are significant in high-κ oxide/semiconductor interfaces and crucial for device performance evaluation. An efficient analytical model is, therefore, due for characterizing the electrostatic and transport behavior of depletion mode GAA MOSFETs that would predict the performance metrics with scaling of process parameters.

In this paper, an analytical drain current model is proposed for symmetric operation of short channel InGaAs GAA MOSFETs that accurately predicts the carrier density under electrostatic conditions as well as computes drain current from depletion to strong inversion under applied drain bias, incorporating interface traps and volume oxide charges. In Sec. II, a quasi-2D Poisson equation is solved in the active region with appropriate boundary conditions to determine the mobile carrier density, facilitating the determination of the quasi-static capacitance–voltage (CV) profile. The drain current is evaluated in Sec. III under the classical drift-diffusion formalism with the inclusion of certain short channel effects such as drain induced barrier lowering (DIBL), threshold voltage roll-off, subthreshold slope degradation, series resistance, channel length modulation, velocity saturation, and mobility degradation due to vertical and lateral electric fields to implicate the underlying physics of short channel operation. The impact of physical process parameters is rigorously investigated with channel length scaling in Sec. IV. The feasibility of high-κ dielectrics to enhance device subthreshold characteristics will also be explored in this section. The excellent match between model results and published experimental reports highlights the accuracy of the proposed model in conjunction with numerical TCAD simulation to validate scaling properties. Section V systematically draws the conclusion of this work.

The symmetric gate-all-around MOSFET under consideration has acceptor doping concentration N_A in the In_1−xGa_xAs channel with equal width (W) and height (H), gate length L, and ALD Al₂O₃ having thickness t_ox, as shown in Fig. 1. The Ga-composition is 0.47 where not stated, and the central nanowire axis is taken as the origin so that the oxide/semiconductor interface is at x = y = ∓W/2.

Under the normal operating regime, the majority of carriers can be neglected, and the gradual channel approximation applies to the quasi-2D Poisson equation of a long channel GAA MOSFET,²⁴ 

Here, ε_s is the semiconductor permittivity, V is the electron quasi-fermi level with reference to the source, ϕ_t = kT/q is the thermal voltage, ϕ_f = ϕ_t ln(N_A/n_i), n_i is the intrinsic carrier density of In_0.53Ga_0.47As, and x and y represent the width and height directions, respectively. Due to the symmetric cross section, the electric field is identical in magnitude in both x and y directions, verified by 3D numerical simulations. Thus, the simplifying assumption $dϕdx=dϕdy$ applies to (1) leading to

Since (2) does not possess a closed form solution, by integrating once from the central nanowire axis to the oxide/semiconductor interface with appropriate boundary conditions,^24,25 which are ϕ = ϕ₀, $dϕdx=0$ at the central nanowire axis, ϕ = ϕ_s, and $dϕdx=Es$ at the interface, we get

where ϕ_s and ϕ₀ are the surface and center potential of the nanowire MOSFET, respectively. For the sake of simplicity, we consider α = (ϕ_s − ϕ₀)/ϕ_t as the normalized difference of potential, which, in deep depletion, takes a constant value (α_st) under the full depletion approximation (FDA) in the Poisson equation,

where Q_b is the total fixed charge per unit length.

Although the use of constant α_st well above the threshold is a crude approximation,²³ by relying on a coarse finite difference method, an exact expression of the normalized difference of potential above the threshold can be written in terms of the principle branch of the Lambert function,²⁶ 

Using Eq. (5) in (3) helps reduce the surface electric field in terms of ϕ_s only,

Since the space charge density per unit length in the semiconductor is given by Q_s = 4Wε_sE_s, the mobile charge density per unit length follows from the difference in space charge density and fixed charge density.

Despite advancement in ALD techniques, significant trap defects exist at the high-κ oxide/semiconductor interface, which are accounted from the flat D_it profile through the relation²² 

where E_i = E₀ and E_j = E_F if E_F lies above E₀ and vice versa. E₀ is the charge neutrality level of interface defects (∼0.27 eV), which are mainly of donor type for Al₂O₃.²⁷ The presence of positive fixed oxide charges Q_f distributed throughout the gate dielectric affects the flat-band voltage V_fb by

where ϕ_ms is the metal–semiconductor work function difference and C_ox is the oxide capacitance per unit length defined as

Here, C_fr = 2(ε_ox/π)ln(1 + d₁/d₂) is the fringing capacitance resulting from the perpendicular plate alignment in the corners of the GAA MOSFET.²⁸ 

Applying Gauss’s law to the oxide/semiconductor interface and using (6) relate the gate voltage to the surface potential by

The solution of (10) facilitates the evaluation of surface potential necessary for determining mobile charge that is modulated under electrostatic conditions and takes part in carrier transport,

The approximation of the Lambert function given by (12) remarkably improves the speed of the solution in (10) with only a minor error introduced in the threshold region, as will be discussed in Sec. IV,²⁹ 

The quasi-static capacitance–voltage profile is obtained from gated mobile charge density by differentiating Q_n with respect to gate voltage,

where C_G depends implicitly on physical dimensions, material properties, and the gate dielectric.

The core drain current of the short channel GAA transistor is expressed in terms of the following integral:

where μ_eff and L_eff are effective mobility and channel length, respectively, after accounting for mobility degradation and channel length modulation and Δϕ_min is the minimum potential barrier change in the conduction channel as elaborated below.

The potential barrier along the conduction path is minimum in the leakiest path of the transistor, which lies in the central nanowire axis of the MOSFET. The degree of SCE affecting threshold voltage (V_th) roll-off, DIBL, and subthreshold slope degradation of the short channel transistor can be modeled by the change in this minimum potential obtained from the solution of the quasi-2D Poisson equation written in terms of ϕ₀ under FDA as follows:³⁰ 

where the characteristic natural length of the symmetric GAA MOSFET is defined as² 

Here, the natural length of the GAA MOSFET has been derived from the parabolic potential model, which was proposed by Suzuki et al.³¹ and Auth and Plummer³² and further corroborated by the authors of Refs. 30, 33, and 34. By applying boundary conditions ϕ₀(0) = V_bi at the source end and ϕ₀(L) = V_bi + V_DS at the drain end, (15) is solved to obtain

where the point of minimum potential is given by

Here, the built-in potential $Vbi=ϕt⁡lnNDNA/ni2$ depends on the concentration of the heavily doped source/drain region N_D,

It is to be noted that (18) is valid in the subthreshold region only. Hence, to determine z_min, the gate voltage is limited to threshold voltage.

At low V_DS, the approximation A ≈ B leads to z_min = L/2 and facilitates the determination of threshold voltage for short channel GAA transistors (V_th,SC) given by

where V_th,LC is the threshold voltage of the long channel GAA MOSFET obtained from the double derivative method in Ref. 25 and ϕ_{min, th} is the threshold voltage roll-off due to scaling of the gate length, evaluated by considering ϕ_{min, th} as the difference between the long channel minimum potential and the shift in minimum potential induced by the SCE,³³ 

The difference between (17) and (21) provides the change in minimum potential barrier Δϕ_min necessary for SCE correction in the core transport model (14).

The drain saturation voltage of long channel devices V_GT = V_GS − V_th,LC is no longer followed by short channel transistors due to velocity saturation. An empirical relation, derived from numerous simulations for channel lengths lower than 300 nm, models the drain saturation voltage as³⁵ 

where η is an adjusting parameter and v_sat is the saturation velocity. The drain saturation voltage V_DS,sat(SC) is gradually limited from its long channel counterpart by the relation

An effective drain voltage is used in the core model where the drain voltage from the terminal is restricted to drain saturation voltage by the continuous expression

The degradation in mobility in the active region, resulting from the high lateral field due to proximity of the drain terminal to source end and surface scattering induced by the vertical electric field, is incorporated into the transport model by the effective mobility expression given by

Here, σ is a constant parameter, which takes into account the carrier–carrier scattering in the channel region arising from the high lateral field, and μ₁ is the vertical field mobility degradation expressed in terms of low field mobility μ₀ and mobility degradation coefficient θ as

The mobility degradation coefficient is calibrated with experimental reports¹⁹ such that contributions from surface scattering are incorporated into the model. Consequently, the corner effect in the GAA structure becomes strong at high overdrive voltage. The hyperbolic tangent factor in the denominator of (28) brings about this degradation at high gate field, thus mitigating the complexity of the numerical simulation.

As drain voltage exceeds saturation voltage, the short channel device suffers from reduced L due to extension of the drain-channel depletion region. For V_DS > V_DS,sat, the effective channel length then follows³³ 

where κ is a fitting parameter and β = V_DS − V_DS,sat.

The reduction in drain current in the saturation regime is attributed to the presence of parasitic resistance causing a voltage drop between the gate–source and the drain–source region. The total resistance can then be expressed in terms of channel resistance R_ch and parasitic resistance R_S(R_D) at the source (drain) end as³⁶ 

Taking (14) to be the drain current without parasitic resistance and using R_ch = V_DS,eff/I_D, we get the final drain current model (I_D′) in the form

The results derived from the analytical model in Secs. II and III were compared with the experimental demonstration in Ref. 19 and further corroborated with 3D numerical simulations using the Synopsis tool.³⁸ In order to capture the physical effects inherent in the inversion mode operation of the short channel GAA MOSFET, various models were used in the TCAD simulation. This includes mobility degradation at the interface due to surface roughness and surface phonon and carrier–carrier scattering, which stem from the doping within the channel region. Apart from mobility degradation, the velocity saturation model and trap charge specification at the semiconductor–oxide interface and fixed oxide charges distributed throughout the gate dielectric were utilized. Generation–recombination processes account for exchange of carriers between the conduction and valence band. They are very important for device physics, hence these were implemented during device simulation. As oxide thickness, channel width, and gate length are scaled toward the deca-nanometer regime, certain non-ideal effects come into play and degrade subthreshold characteristics. These effects are included by invoking the density gradient quantization model for important quantum effects. Table I lists the relevant physical process parameters used throughout this work for validation. As can be seen in Fig. 2(a), the mobile charge density predicted by the model, after inclusion of interface trap defects and a positive fixed oxide charge of ∼9 × 10¹⁸ cm⁻³ distributed throughout the volume of oxide, matches well with that extracted at mid-channel from simulation. The use of (12) in the solution of mobile charge dramatically enhances the computation speed of the model with only an error of about 0.51% error introduced in the transition from threshold to weak inversion.

The effect of physical dimension and material properties on CV characteristics is illustrated in Fig. 3. The model accounts for minority carrier concentration only with the CV profile decreasing to zero in the depletion mode and saturating to oxide capacitance in the strong inversion regime. As dictated by (9), the oxide capacitance is highest for a larger fin width and the thinnest gate oxide. Figure 3(b) reveals that the electrostatic behavior of a GAA MOSFET depends strongly on fin width in comparison to oxide thickness. The analysis of devices with a fin width smaller than 10 nm is restricted from the proposed model due to negligence of the quantum effect. With inclusion of the density gradient quantization model in TCAD, the simulation results reflect a rightward shift in the CV curve for a fin width of 10 nm, indicating the impact of quantum effect in threshold voltage shift near the subthreshold region and a degradation of gate capacitance in the strong inversion regime. On the contrary, channel doping and the Ga-mole fraction affects the CV profile in the depletion region only. For channel doping above 1 × 10¹⁷ cm⁻³, the shift in the CV curve is more prominent. At higher doping levels, the GAA MOSFET may enter partial depletion, requiring greater gate bias to create channel inversion. A decrease in the Ga mole fraction causes a leftward shift in CV transition, which is expected from the decreased bandgap of In_1−xGa_xAs, facilitating the electron transition from the valence band to the conduction band at a reduced gate bias, as shown in Fig. 3(d).

The transfer characteristics obtained from the proposed model are displayed in Fig. 4. The drain current and extrinsic transconductance g_m are normalized by the active region perimeter (2W + 2H). Some of the transport model parameters used to calibrate the model with published experimental reports are shown in Table II, which accounts for velocity saturation, mobility degradation, channel length modulation, and series resistance. The numerical solution of (10) provides a smooth transition in the threshold regime, which is further confirmed by continuous g_m, producing distinct peaks near the threshold point [Fig. 4(b)]. The incorporation of interface trap charge is essential in evaluating subthreshold performance metrics, as portrayed in Fig. 4(c). The threshold voltage in DIBL evaluation is extracted from the I_D–V_G plot at a constant current level of 2 μA/μm due to high drain junction leakage current. The subthreshold slope (SS) obtained from the inverse of the steepest slope of transfer characteristics and DIBL at different gate lengths falls in the range of reported data, providing a precedent for comparing off-state performance of next generation GAA transistors.

The output characteristics of the GAA transistor match well with the published report¹⁹ in both linear and saturation regimes. From Fig. 5(a), it can be seen that an on-resistance of 1160 Ω μm is obtained from the initial slope of the I_D–V_D curve at V_GS = 2 V. The continuity of the output characteristics is reflected from the gradual transition in output conductance, as illustrated in Fig. 5(b).

Before delving into the scaling properties of GAA transistors, the degree of SCE affecting such devices are explored semi-analytically in both on and off states. Double-gate MOSFETs suffer from severe SCEs as the W/L ratio approaches unity.⁴⁰ Gate-all-around MOSFETs, on the other hand, provide better off-state performance in this regard, with DIBL and SS demonstrating roughly a proportional variation with the W/L ratio. As shown in Fig. 6, for the range of fin width shown in Table I, the maximum W/L ratio studied was 0.8 after which the DIBL and SS stray away from the linear relation. The impact of SCE on the subthreshold slope is even more at higher drain bias, which is evident from the sparsity of SS from the best fit linear graph in Fig. 6(b). The scaling behavior of drain current in the on-state of the transistor is displayed by tracing the maximum drain current from submicron to long channel lengths, as shown in Fig. 6(c). In the absence of non-ideal effects, the GAA transistor could reach drain current as high as 1 mA/μm at a gate length of around 40 nm. However, saturation induced by the SCE limits the channel current from reaching near ideal values.

The proposed model accurately describes the transport phenomenon of III–V channel devices with scaling of physical process parameters. The transfer characteristics of III–V GAA MOSFETs for various fin widths are presented in Fig. 7. The saturation levels of the normalized drain current in the strong inversion region is less dependent on fin width, although fin width scaling affects threshold characteristics strongly and indicates an improvement in threshold behavior by shifting the transition from threshold to weak inversion to the right. This is attributed to volume inversion of the III–V channel caused by confinement of charge carriers at sub-nanometer dimensions, which otherwise would require further reduction in fin width for silicon technology. The GaAs gate-all-around MOSFET has a lower off-current and better I_on/I_off ratio, arising from larger effective mass along the transport direction than InGaAs, which suppresses the drain-junction leakage current.⁴¹ On the contrary, the lower saturation current of similar GaAs devices in the strong inversion region can be elaborated by the proportional dependence of drive current (I_D) on the product of channel mobility and inversion capacitance (μC_inv).⁴² Although the larger density of states favors GaAs devices with a greater inversion capacitance, it is offset by the lower channel mobility of the GaAs channel, resulting in a low on-state current, as depicted in Fig. 7(a). These results are in coherence with previous reports, thus corroborating the efficacy of the proposed model in determining the scaling trend of physical dimensions for a range of III–V compounds as channel materials in GAA transistors. The inset figure reveals the finding that that the total current of a wider nanowire MOSFET is more, as expected, due to increased surface carriers near the oxide/semiconductor interface. There is only a slight increase in the g_m peak for both InGaAs and GaAs channels, as evidenced from Fig. 7(b), which can be further enhanced by scaling to deca-nanometer dimension, the analysis of which is restricted from the proposed model due to negligence of quantum effects.²⁰ Nevertheless, the excellent match between numerical simulations having a quantization model and analytical results justify the relaxation of quantum effect incorporation into the proposed model for the range of dimension under study.

Figure 8 explores the trend in transfer characteristics with oxide thickness variation. For the sake of benchmarking, an initial oxide thickness of 10 nm was used for a gate length of 50 nm, resulting in an EOT of 4.5 nm, which is much larger than the ITRS guideline for device dimension.⁴³ However, we explored the trend of oxide scaling with EOT around 1 nm in compliance with the proposition of ITRS. It was found that increasing the gate oxide thickness induces a reduction in channel current, besides lowering the threshold voltage. The existence of a cross-over in the transfer characteristics was previously observed for long channel devices with a wrap-around gate.⁴⁴ This phenomenon is extant in short channel transistors as well, regardless of the III–V channel material, occurring near the threshold region of doped nanowire MOSFETs, and serves as an invariant point, particularly important where oxide thickness variation could not be strictly controlled due to process limitations. The g_m peak increases by 2.4 times by reducing the gate dielectric thickness from 10 nm to 2.5 nm, as portrayed in Figs. 8(b) and 8(c). This highlights a potential scope for EOT scaling, which, alternately, can be achieved by introducing high-κ dielectrics into the MOS transistor.

Figure 9 gives us an elaborate comparative analysis of the impact of dimension scaling on the subthreshold performance of GAA nanowire MOSFETs. Due to the presence of SCE, the minimum gate bias required for turning on the MOSFET is lowered as the channel length is scaled down. From Figs. 9(a) and 9(d), it is observed that fin width causes a greater threshold voltage roll-off at sub-nanometer gate lengths. The loss of gate control over electrostatic charges in thicker nanowire means that threshold voltage decreases drastically with gate length reduction. The effect of scaling on DIBL for various fin width and oxide thicknesses is displayed in Figs. 9(b) and 9(e). The effect of DIBL is severe for nanowires with a larger fin width, which is particularly inherited from the aggravated threshold voltage roll-off described earlier, and only slight improvement is obtained by reduction of fin width to practical limits. On the other hand, a dramatic enhancement of DIBL is identified for GAA MOSFETs with thinner oxide thicknesses. A similar variation in SS is observed from dimension scaling, where the minimum slope of the InGaAs MOSFET is far from the ideal SS of 60 mV/dec. The poor DIBL and SS are attributed to the high interface trap density between the Al₂O₃/InGaAs interface. This could be overcome by stacking the gate oxide with LaAlO₃, as was successfully demonstrated in Ref. 3.

It is evident that the ultimate scalability of GAA MOSFETs can be achieved by incorporating high-κ dielectrics having suitable integrability with the channel material. Although ALD Al₂O₃ is reported to have the best interface quality with InGaAs, the performance of such GAA transistors is limited by a poor I_on/I_off ratio resulting from high drain junction leakage current. The switching efficiency (Q = gm/SS) is an important figure of merit to quantify the potential of inserting III–V channel material in CMOS technology that evaluates the I_on-vs-I_off metric to capture the trade-off between dynamic switching speed and standby power.⁴⁵ The incorporation of LaAlO₃ or HfO₂ results in better switching efficiency, as clarified by Fig. 10. A high D_it of 12 × 10¹²/cm²eV at ∼0.15 eV below the conduction band was adopted for HfO₂ from published reports into the analytical framework.^46,47 Figure 11 illustrates a radar plot comparing the key features and benefits of using HfO₂ over Al₂O₃ as the gate dielectric. At low drain bias, the subthreshold behavior is remarkably improved by replacing the gate oxide with HfO₂, reducing DIBL, subthreshold slope, and threshold voltage roll-off to a greater extent. An increase in I_max indicates the superior current drivability in the on-state of the GAA transistor with a high-κ dielectric. A switching figure of merit Q(=g_m/SS) of 0.82 (μs/μm)/(mV/dec) is obtained from using HfO₂, resulting in an improvement of 2.5 times over Al₂O₃. The high switching efficiency indicates InGaAs MOSFETs as a potential candidate for switching application and logic devices.

A capacitance–voltage and analytical drain current model is proposed in this work, catered for InGaAs with inclusion of interface defects and trap charges existing near the oxide/semiconductor interface. Certain non-ideal effects are included to emulate the SCEs in ultrascaled transistors. The model parameters have been calibrated with published reports based on symmetric InGaAs MOSFETs. An extensive analysis of the GAA transistor is presented with variation in physical process parameters. Subthreshold performance metrics such as threshold voltage roll-off, DIBL, and subthreshold slope have been thoroughly investigated. Furthermore, the benefits of EOT scaling and integration of a high-κ dielectric are explored to realize the scalability of GAA MOSFETs in the sub-nanometer domain, making them a potential candidate for switching and logic applications. The analysis presented in this work will provide the necessary platform for examination of more complex nanosheet structures.

This work was carried out in the Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology (BUET). The authors gratefully acknowledge the support and facilities provided by BUET.

The data that support the findings of this study are available from the corresponding author upon reasonable request.