Fabrication of a high-speed plasmonic reflection/transmission modulator

Ever-increasing demands for high-speed data throughput in telecommunication systems motivate high-speed, broadband optical modulators in integrated electro-optic systems. Optical modulators based on Si photonics but exploiting 2D materials and/or plasmonics are particularly promising due to their potential to overcome speed, bandwidth, and size trade-offs, and their integration possibilities with ancillary electronics.^1–15,29

Surface plasmon modulators, in particular, can provide fast and effective modulation by using surface plasmon-polaritons (SPPs) and their unique properties in interacting with the modulation medium. The dispersive properties of metals (e.g., Au and Ag) at optical frequencies, particularly pertaining to the negative real part of permittivity, are such that visible and near-infrared light may excite SPPs at the surface. SPPs are transverse-magnetic (TM) polarized surface waves where the magnetic field is in the plane of the metal surface and is perpendicular to the direction of propagation, which is along the metal–dielectric interface. The electric field has a weak longitudinal component but a strong transverse component perpendicular to the metal surface. This field component is enhanced relative to the exciting field, which leads to strong light–matter interaction—a motivating factor for the use of SPPs in electro-optic modulators. The wavenumber of an SPP is larger than that of freely propagating light, which makes direct coupling impossible. Coupling occurs in the presence of, e.g., surface roughness, gratings, or prisms, which can manipulate the wavenumber of the incident radiation to match that of the SPP.

Active control of SPPs, either electrically, optically, or via temperature, forms the basis for plasmonic switches and modulators. Notably, the metallic structures supporting SPPs can also be used as device driving electrodes (current and voltage) to ensure strong overlap between the SPP fields and the active region of the device. Modulation depths of 80% and switching times on the order of picoseconds are expected.¹⁶ Plasmonic devices also fulfill the need for achieving a nanometer-scale footprint, high-speed, and low power consumption.^17,18,30,31 Depending on the property of light that is modulated, optical modulators are classified into different categories, such as amplitude modulators,⁶ phase modulators,^5,7,9,13 polarization modulators,¹³ and wavelength modulators.⁵ The performance of a modulator is usually characterized by modulation speed, modulation depth, operating wavelength, power consumption, and insertion loss.

This paper describes the fabrication and realization of a plasmonic modulator that can operate at high speed in reflection and/or transmission. This paper is based on previous work,^14,19 by introducing front-side coplanar electrodes compatible with microwave probes, thereby enabling high-speed operation and operation in transmission, and by introducing an inter-metal dielectric to reduce parasitic contact pad capacitance. Nanofabrication methods are discussed in detail along with fabrication results.

A plasmonic reflection/transmission modulator, designed as a metal–oxide–semiconductor (MOS) capacitor, excited by a p-polarized continuous-wave optical beam, and electrically controlled by an external electrical drive signal, is shown schematically in Fig. 1. The device consists of a circular thin Au film (t = 20 nm) as a “plasmonic patch,” on a thin (d = 5 nm) hafnium dioxide (HfO₂) layer, grown on a highly p-doped Si substrate via atomic layer deposition (ALD). The thin Au film, the HfO₂ layer, and the p-doped Si substrate form a metal–oxide–semiconductor (MOS) structure. Au ridges forming a grating are overlaid on the thin Au film, and they couple the incident light to SPPs propagating along the bottom surface of the Au film, with SPP fields penetrating through the HfO₂ and into the Si substrate. The grating pitch varies from $Λ$ = 420 nm to 480 nm. Its duty cycle is fixed at D = 50%, and the thickness of the ridges at H = 80 nm. The gratings are covered with a 700 nm thick layer of polymer (SU-8) as a transparent dielectric interlayer. In order to access the thin Au film electrically, a metal contact pad is deposited on the dielectric layer. A via extends from the metal contact pad through the SU-8 layer down to a small finger extending from the thin Au film. A pair of separate larger vias extends from the top contact metal layer down to Ohmic pads in direct contact with the silicon surface, which acts as the ground terminals of the device. The layout of the contact pads was selected to accommodate the standard pitch of microwave ground-signal-ground (GSG) probes. The dielectric interlayer ensures that the electrical performance of the MOS capacitor is not compromised by excess parasitic capacitance from the contact metal to the silicon substrate, and it passivates the device.

A nanoscale grating structure (first order) is used to couple the incident light to the SPPs propagating along the MOS interfaces. Tightly confined SPPs are sensitive to refractive index changes in the modulation region in the semiconductor along the oxide surface. Accumulation and depletion of carriers in this region, following the application of an external electrical signal to the MOS capacitor, changes the effective refractive index of the SPPs. This in turn alters the coupling efficiency of SPPs, and, thus, the modulation intensity of the reflected and transmitted light. In essence, the voltage applied at the electrical contacts is used to modify the reflectance and transmittance of the device, which permits intensity modulation of the reflected and transmitted beams.

Numerical methods were used to model a cross section of the device and determine the design parameters of the structure for operation at λ₀ = 1550 nm.²⁰ An optimized design maximizes the sensitivity of the SPPs to refractive index perturbations in a thin region of semiconductor along the oxide, and, thus, the coupling efficiency of the incident beam to the SPPs. Computations via the transfer matrix method reveal that as the thickness of the oxide and metal decreases, the differential refractive index, Δn_eff, increases due to increasing overlap of the SPP fields with the perturbation. Taking into account fabrication limitations, the thickness of the metal was chosen as t = 20 nm, and the thickness of oxide was chosen as d = 5 nm.

Using the momentum conservation equation for gratings,

an initial value for the grating period was obtained as $Λ$ = 420 nm–480 nm, where broadside excitation along the surface normal and a first-order grating are assumed. The 2D finite-difference time-domain (FDTD) method was used to model the optical performance of the structure, yielding the reflectance, transmittance, absorptance, and grating coupling coefficient.²⁰ 

Figure 2 shows the flow of the major fabrication process steps that were developed and applied. In summary, single-side polished, prime grade, p-doped Si wafers were purchased. A thin film of HfO₂ was deposited on the wafers by atomic layer deposition (Namlab GmbH, Dresden, Germany). Thin Au films (plasmonic patches) were deposited on HfO₂, followed by etching of HfO₂ in select locations to enable Pt-capped Al Ohmic contacts to the p-Si substrate as ground terminals. Au nanogratings were then defined by e-beam lithography, evaporation, and lift-off, centered on the plasmonic patches. A film of SU-8 2000.5 was deposited as the dielectric layer, and via holes were created through the film of SU-8 by exposure and development. Finally, Cu/Cr contact pads were deposited on SU-8, and the vias were metalized to provide electrical access to signal and ground contacts on the device.

A bilayer lift-off process was carried out to define Au circular plasmonic patches of various diameters (3 µm, 5 µm, 11 µm, 17 µm, 22 µm, 28 µm, and 56 µm) on HfO₂. For this purpose, a 2-in. p-doped Si wafer (P/B, ρ = 0.001 $Ω$ cm–0.005 $Ω$ cm) was used, with a 5 ± 0.1 nm thick film of HfO₂ on its surface. The step-by-step process is summarized in Tables I and II.

Microchem LOR 1A lift-off resist was spun on the substrate surface (HfO₂) at 6000 rpm and baked at 190 °C for 5 min. Megaposit SPR 955-CM photoresist (PR) was then spun on LOR 1A at 6000 rpm and baked at 90 °C for 3 min. Afterward, the bilayer resist stack was exposed to 84 mJ of UV light, using a photomask in an OAI Model 204IR mask aligner. Three I-line (λ₀ = 365 nm) bandpass filters were used to optimize pattern resolution. Using a stack of three filters allowed for more precise control over the exposure energy. The sample was then immersed in developer Microposit MF CD-26 for 60 s. A 20 nm thick layer of Au was deposited on a 0.3 nm thick layer of Ti used to promote adhesion. Both metals were deposited via thermal evaporation using an Angstrom Nexdep Evaporator. The unexposed parts of the bilayer resist stack, along with the Au film covering them, were lifted-off by immersing the sample in Remover PG (Microchem).

To establish Ohmic contacts, metal must be in direct contact with the semiconductor substrate. Therefore, a buffered oxide etch (BOE) process was practiced to open windows in HfO₂ to let the Ohmic metal make direct contact with the p-Si substrate. A bilayer stack of SPR 955 on LOR 1A was utilized to etch the windows in HfO₂, then lift-off the evaporated Ohmic metals by self-aligned processes (i.e., the same lithography stack was used to carry out both processes). The PR was exposed, using the same parameters as shown in Table II, and developed by immersion into MF CD-26 for 60 s. At this stage, the sample surface was covered with the bilayer resist stack except for the openings where HfO₂ must be etched in order to realize the Ohmic contacts. The sample was then immersed in a 5% diluted hydrofluoric (HF) acid solution for 30 s, followed by a de-ionized (DI) H₂O rinse and N₂ blow. The sample was then immediately loaded into the evaporator. Al was chosen as the Ohmic contact metal due to its high conductivity, low Ohmic contact resistance to p-type Si, and good adhesion to Si.²¹ Thus, a 100 nm thick layer of Al, capped by a 20 nm thick layer of Pt, was e-beam evaporated, and lifted-off. Pt was introduced as a conductive protective layer of Al during subsequent process steps. See supplementary material for the process flow and a summary of steps for the realization of Ohmic contacts.

Nanogratings were deposited on the plasmonic surfaces in order to achieve coupling of the incident beam to SPPs. The dimensions of the nanogratings were selected to optimize the optical performance of the modulators (Λ = 420 nm–480 nm, H = 80 nm, D = 50%).²⁰ The size of the Au plasmonic patches affects the metal–oxide–semiconductor (MOS) capacitance of the structures and the electrical bandwidth of the devices. Thus, it is important for the patch and grating dimensions to be as close as possible to the designed dimensions. Electron beam lithography, overlaid to the existing plasmonic patches, was used to produce gratings of high resolution. Au deposition was then done by thermal evaporation, followed by lift-off. The protocol for the fabrication of nanogratings is summarized in Table III.

A dielectric interlayer is required between the top layer contact metal and the device level to ensure that the electrical performance of the MOS capacitor is not compromised by excess parasitic capacitance to the silicon substrate. It also provides some measure of protection to the grating surface. SU-8 2000.5 was selected for this purpose.

When exposed to UV light and subsequently baked, SU-8 becomes cross-linked and insoluble in liquid developers. SU-8 has very high optical transparency at wavelengths above λ₀ = 360 nm, which makes it optically non-invasive to the performance of our devices. SU-8 is best suited for permanent applications where it is imaged, developed, cured, and retained. It comes in different viscosities. The least viscous type, SU-8 2000.5, was used for this application, since the desired film thickness, according to the numerical optimization,²⁰ is ∼700 nm, which can be achieved with SU-8 2000.5.

The first step was spin coating SU-8 2000.5 on the wafer bearing the plasmonic patches and gratings, as well as the Ohmic pads. The second step was a soft bake (SB), where the sample was placed on a hotplate at 65 °C for 5 min. A temperature ramp-up was then used to reach 95 °C, where the sample was left for another 5 min. A ramp-down was then performed to bring the sample temperature to 50 °C, bringing the total time on the hotplate to 25 min. The soft bake is necessary to remove the solvent from the SU-8. Temperatures, bake-times, and ramps are important to reduce stress formation and cracks in the film.

After a 10 min cool-down, SU-8 was exposed to UV light, using a bright-field photomask to define via holes in the layer. An I-line filter was used to increase the pattern resolution. As a result, SU-8 cross-linking was initiated where exposed. In order to avoid over-exposure around the edges, SU-8 was exposed with the minimum required energy. Over-exposure causes SU-8 to cross-link around the edges, where it is expected to be removed and, thus, perturbing dimensions from what is desired. Hard contact was used in the mask aligner in order to minimize the gap between the photomask and the sample.

Post-exposure bake (PEB) is necessary to complete the cross-linking of the SU-8. The sample was placed on a perfectly flat hot plate set at 90 °C for 1 min. The temperature was then ramped up to 105 °C, and the sample was baked for 1 min. The hot plate temperature was then ramped down to 75 °C, at which point the sample was removed from the hot plate.

An SU-8 developer was used to develop the sample. The best results were achieved using the vertical positioning of the wafer in the developer for 3 min, followed by two intervals of 10 s in an ultrasonic bath at 80 KHz and 30% power. Hard bake (HB) is required if further processes are to be done on SU-8, which is the case here. Thus, the sample was baked for 30 min on a hot plate at 120 °C. The sample was then flood exposed for 30 s to improve the adhesion of the next layer metal to SU-8. See the supplementary material for the fabrication flow and a summary of steps in processing the SU-8 layer.

It was found that defining via holes in SU-8 depends significantly on the size and geometry of the holes, as well as the thickness of the SU-8 layer. For a circular hole, if its diameter is small and the thickness of SU-8 layer is larger than the diameter, a bright spot (“Poisson spot”²²) forms in the layer of SU-8 during exposure due to diffraction. Specifically, when a bright-field photomask bearing dark disks is illuminated with a collimated exposure beam from the mask aligner, a bright spot appears behind the center of the dark disks on the photomask within the SU-8 layer where the via holes are to be developed. The bright spot, located along the central axis of the dark disk, inside the SU-8, causes activation of the photoactive component therein and only partial development of the hole. The result was observed as pillars formed at the center of the smallest diameter via holes.

Numerical modeling was carried out using Lumerical FDTD to verify this observation. A layer of SU-8 (700 nm thick) was assumed on a 1.5 µm thick Si substrate. A glass mask with 100 nm thick Cr masking disks of various diameters covered the SU-8 layer. The structure was illuminated from the top with a plane wave of wavelength 365 nm. The transmittance through a 100 nm film of Cr at the wavelength of interest was close to zero. Figure 3 plots the distribution of the electric field magnitude over the cross section of the SU-8 layer and the masking disks. An interference pattern is visible throughout the SU-8 layer due to the use of coherent illumination in the modeling—the actual illumination in the mask aligner is filtered but incoherent, so a well-defined interference pattern is not expected. The field diffracted below the mask disk clearly forms a Poisson’s spot, observed to vary with the disk diameter and becoming significant for a small diameter. The Poisson’s spot will not be as well-defined using the mask aligner, again due to incoherent illumination, but will nonetheless be present.

In another set of simulations, the same structure was studied, while the disk diameter was fixed at 2 µm, and the thickness of the SU-8 layer was varied from 0.4 µm to 3 µm. The Poisson’s spot becomes more evident as the thickness of the SU-8 layer increases, as shown in Fig. 4. Figure 4(d) plots the field distribution in the case where the Si layer is removed and replaced with an absorbing boundary condition (perfectly matched layer) in order to visualize the distribution without interference.

It is evident from these computations (Figs. 3 and 4) that disk diameters less than 2 µm can produce a significant Poisson’s spot in SU-8 layers that are about 700 µm or thicker. Thus, our via hole design was selected as a rectangular trench of dimensions 4 µm × 10 µm².

In order to facilitate electrical probing of devices and metalize the via holes, relatively thick, large contact pads are required. A bilayer lift-off process was used to fabricate signal and ground contact pads. This process was, in principal, very similar to that used to create the Au plasmonic patches. However, LOR 1A was replaced by the much more viscous LOR 10B lift-off resist to provide a thicker resist stack enabling lift-off of a thick contact metal layer. It is important to carefully align this layer in order to metalize all via holes and achieve contact with the modulator devices and their Ohmic contacts. See the supplementary material for the process flow and a summary of steps.

Following the steps in Sec. II B, plasmonic modulator devices were successfully fabricated. Figure 5(a) shows a microscopy image of a plasmonic patch along with its nearby Ohmic contact pads, metalized and lifted-off. Alignment-marks are also shown in this image. These are to facilitate the alignment of a perpendicularly incident optical beam to the nanogratings during optical tests. Figures 5(b) and 5(c) show an atomic force microscopy (AFM) scan of an Ohmic contact pad and its associated cross-sectional analysis, respectively. The Al Ohmic pads were 93.4 nm thick, with a root mean square (rms) roughness of 1.5 nm, while the target thickness was 100 nm. However, this small difference may be neglected as it does not affect the performance of the device.

At this stage, current–voltage (I–V) measurements were performed to verify the Ohmic contacts with the semiconductor. For this purpose, external probes were used to apply voltage to an arbitrary Ohmic pad, while another nearby pad was grounded. The applied voltage was varied between −1 V and 1 V, in steps of 0.1 V, and the resulting current was measured for various signal to ground pad distances (the maximum current allowed was set to 100 mA). A typical I–V characteristic is shown in Fig. 6, where a linear relationship between current and voltage is observed, characteristic of an Ohmic contact. The resistance, taken as the inverse slope of this I–V characteristic, is 9.66 $Ω$⁠, obtained for two adjacent Ohmic pads, 225 µm apart, center to center. A probing test was performed to determine the resistance of the test setup by directly connecting the two test probes. The set-up resistance was measured to be 5.3 $Ω$⁠, which was used as a calibration value. Thus, the total contact resistance is 4.36 $Ω$⁠.

An equivalent circuit model of the contacts, shown in the inset of Fig. 6, was used to represent measurements between an adjacent pair of contact pads. The total series resistance of this model, R_s, is

The resistance of a single Al/p-Si Ohmic contact is denoted by R_Al–Si. All other resistances in this model (R_Pt, R_Al, and R_Si) are computed using

where ρ is the resistivity of the material for which the resistance is computed, L is the length of the current path, and A_res is the surface area of the contact pads, the design of which produces an area of 4 × 10³µm². The bulk resistivity of Pt and Al was used, along with ρ = 0.005 $Ω$ cm for heavily p-doped Si. Setting R_s to the total measured value (R_s = 4.36 $Ω$⁠) and isolating yields, the contact resistance at the Al/p–Si interface as R_Al–Si = 0.77 $Ω$⁠.

Capacitance–voltage (C–V) measurements were also obtained to characterize the electronic performance of the MOS capacitors forming the Au–HfO₂–Si structure. Figure 7 gives a typical high-frequency measurement for a plasmonic patch and a neighboring ground contact, obtained using an HP 4284a LCR meter at a frequency of f = 1 MHz and applied AC voltage of v_s = 5 mV (maximum value). The accumulation capacitance C_ox is determined from Fig. 7 to be 40 pF. The diameter of the circular plasmonic patch probed was 56 µm. Therefore, given the thickness of the oxide layer as d ∼ 5 nm (verified independently by AFM), the relative permittivity of the oxide layer is found to be ε_ox = 9.18 by fitting to

where A_c = 9852 µm² is the area of the capacitor.

C_ox consists of the capacitance over the film of hafnia C_HfO2 in series with a capacitance over a layer of native SiO₂, C_SiO2, present on Si prior to ALD of HfO₂. Assuming the thickness of the SiO₂ layer to be t_SiO2 ∼ 1 nm, and its relative permittivity as ε_SiO2 = 3.9, using Eq. (4) yields C_SiO2 = 85 pF. From this value, C_HfO2 = 75.5 pF was obtained via

Subsequently, the relative permittivity of a 4 nm HfO₂ layer was determined as ε_HfO2 = 14, following Eq. (4). This is in the range of values reported in Refs. 14, and 23–25 (ε_HfO2 = 12–25). Thus, ε_ox is taken as an equivalent relative permittivity for the oxide stack.

The maximum depletion width x_dT was then calculated²⁶ to be 8.2 × 10⁻⁷ cm for our highly p-doped Si substrate (2.13 × 10¹⁹ cm⁻³). The minimum capacitance per unit area C′_min, which is defined at the threshold inversion point where the maximum depletion width is reached but the inversion charge density is essentially zero, can be obtained via²⁶ 

where ε_s = 11.7 is the relative permittivity of the semiconductor, Si. Thus, C_min = C′_min × A_c = 17.6 pF is obtained, which agrees with the minimum capacitance measured in Fig. 7.

The point on the C–V curve, which corresponds to the flat-band condition V_FB, is of interest. The flat-band capacitance per unit area C′_FB is given by²⁶ 

The flat-band capacitance C_FB = C′_FB × A_c = 35 pF is obtained, which yields V_FB = −0.8 V, as shown by the C–V plot in Fig. 7.

The flat-band voltage was then used to determine the equivalent fixed charge per unit area Q′_ss in the HfO₂ layer. In an ideal oxide, with no fixed charges, the flat-band voltage is equal to the metal–semiconductor work function difference ϕ_ms. In a non-ideal situation, the presence of fixed charges in the oxide, introduced during fabrication, affects the flat-band voltage such that

Assuming ϕ_ms = −0.0016 V results in the equivalent fixed charge Q_ss = 3.14 × 10⁻¹¹ C. The equivalent fixed charge per unit area is then Q′_ss = Q_ss/A_c = 1.27 × 10⁻⁶ C/cm², which is comparable to the values reported in Ref. 27.

The C–V characteristic was driven in accumulation beyond the break-down of the oxide, which occurred at a voltage of −5 V (Fig. 7). Given the thickness of the oxide layer as d = 5 nm, this yields a break-down electric field of ∼10 MV cm⁻¹, which is close to the expected value for ALD HfO₂.^14,25,28

The electrical bandwidth of this modulator device is given by

where R_sub is the series resistance through the semiconductor and Ohmic contact pads, R_g is the internal impedance of the generator driving the modulator, and R_L is the load resistance. R_g and R_L are normally assumed to be matched and set to a standard value such as 50 $Ω$⁠. R_s is small compared with R_g, and R_L and is neglected. The electrical bandwidth is then computed for different modulator designs. The smallest plasmonic patch diameter that we have fabricated is 3 µm (large enough to accommodate a diffraction-limited incident optical beam), which yields the maximum bandwidth of BW = 55.4 GHz, for a 5 nm thick oxide layer.

Nanogratings were exposed by e-beam lithography and then metalized as explained in Sec. II B 3. An AFM scan of a grating on an 11 µm diameter plasmonic patch is shown in Fig. 8(a). This scan yields a thickness for the grating ridges of H = 81 nm and for the plasmonic patch of t = 20 nm, which are very close to the target (80 nm and 20 nm, respectively). The rms roughness of the plasmonic patch is in the range of 0.8 nm–0.9 nm, and the rms roughness along the top of a grating ridge is 1.5 nm. Figure 8(b) shows a scanning electron microscopy (SEM) image of a nanograting on a plasmonic patch. The ridge width and the pitch of the grating were measured to be 270 nm and $Λ$ = 460 nm, respectively.

The vias created following the steps in Sec. II B 4 are shown in Fig. 9(a). In this image, a via trench is overlapped with the contact tab of a plasmonic patch, while a bigger via window is opened over the Ohmic contact. Figure 9(b) shows an AFM scan of a via trench opening prior to metalization. The Au tab at the bottom of the via on top of the HfO₂ layer is visible on this AFM scan, as is the topographic contour of the plasmonic patch. The depth of the via is measured to be 709 nm [Fig. 9(c)], which is close to the expected thickness of the SU-8 2000.5 layer (700 nm). This means that the via trench was fully cleared down to the Au (plasmonic patch) and HfO₂ levels. Figure 9(d) shows a zoomed-in view of the cross-sectional analysis in Fig. 9(c), where the thickness of the tab of the plasmonic patch is measured and agrees well with the expected thickness. The rms surface roughness on the tap was 1.06 nm, which is very close to the rms surface roughness of the plasmonic patch (0.8 nm). This also verifies that the via trench was completely cleared.

Finally, Fig. 10(a) shows a microscopy image of the completed device, with signal and ground electric contacts. A SEM image of a completed device is also shown in Fig. 10(b). The physical continuity of the metal signal path down to the plasmonic patch is verified in Fig. 10(c).

Novel plasmonic reflection/transmission intensity modulators were successfully fabricated. An MOS capacitor was exploited as the active region of the modulator device, where a thin film of HfO₂ was sandwiched between a heavily p-doped Si substrate and the Au plasmonic patches, deposited on the oxide layer. Nanogratings are employed to couple the incident beam to the SPPs propagating along the metal–oxide–semiconductor interfaces. Large front-side ground and signal pads were fabricated to allow easy probing of the devices, without obscuring the optical beams. A film of SU8 was utilized as an intermetal dielectric layer to minimize the parasitic capacitance due to the electrical contacts. Complete fabrication details were provided, and the results were given for intermediate structures.

See the supplementary material for detailed steps in the fabrication process flow.

The authors are grateful to Ewa Lisicka-Skrzek and Howard Northfield for helpful discussions.

The data that support the findings of this study are available within the article and its supplementary material.