In this study, we extend the analyses done on sputtered Bi_{x}Se_{1-x} based accumulation mode FETs. Previously, we studied the basic electrical and leakage properties of these FET devices. We extend our analyses to obtain key parameters of the Bi_{x}Se_{1-x} (x = 0.44) film at various gate voltages. We start by extracting the sheet carrier density and bulk mobility for different gate voltages, using the Drude model with the previously obtained semi-empirical relationship between carrier concentration and bulk mobility for Bi_{x}Se_{1-x}. The change in sheet carrier density is a result of accumulation or depletion or majority carriers from the Bi_{x}Se_{1-x}/SiO_{2} interface, which show hysteretic behavior. This allows us to calculate the surface sheet carrier density and the quasi-static capacitance at various gate voltages. We use a simple capacitive model to separate the capacitance originating from the gate and the film bulk. The capacitance from the film bulk is due to the surface charge thickness and is directly dependent on the Debye length. From the change of capacitance, with respect to gate voltage, we were able to identify the characteristics of the conduction band edge and the bulk band gap/Dirac cone.

## INTRODUCTION

Topological insulators (TI) are a key group in condensed matter research. These materials contain ballistic high mobility surface carriers, which can be useful for many applications.^{1–3} Two major application areas are: high electron mobility transistors and spintronics.^{4,5} The key ingredient of the surface states is the topological protection, which is provided by time-reversal symmetry and can eliminate electron backscattering.^{6,7} However, several other surface scattering processes can dominate, making the surface transport similar to that of the bulk.^{8–10} A key bottleneck for TIs is the high-quality thin film deposition/growth techniques required to obtain the topological protection.^{11} This makes the production of the films difficult for CMOS applications. Recently we showed that polycrystalline films grown by simple sputtering techniques could hold the answer to this issue.^{12,13} These polycrystalline films show a slight over concentration of Bismuth (Bi:Se ∼ 0.44:0.56), even though the sputtering target had correct stoichiometric ratio (Bi:Se ∼ 40:60).^{12,13,16} Dc *et al.* shows the cause of this to be a quantum confinement effect in the individual grains of Bismuth Selenide.^{12} Quantum confinement creates additional dispersive bands, which are spin-momentum locked. Further analysis of these dispersive bands show the probability distribution of the electron wavefunction of these bands in real space.^{12} They are concentrated at the edges of the individual grains.^{12} This unique behavior requires thorough analysis of this material and its physics. In the Paper I of this study, we presented the basic transport and material characterizations of Bi_{x}Se_{1-x} based accumulation-mode field effect transistors (FETs).^{14}

In this paper, we attempt to understand the detailed transport properties of these FET devices (Device 1 of Sahu *et al.*: Paper I of this series),^{14} measured in constant source-to-drain current mode. We calculate the carrier concentration and bulk mobility via modified Drude model. We calculate the total capacitance of the device, which is a series combination of the gate dielectric capacitance and the channel capacitance (all the capacitances are defined as capacitance per unit area).

## EXPERIMENTAL RESULTS AND ANALYSIS

We start by first characterizing the carrier concentration and the mobility of the films. The Drude model allows us to write the resistivity using a relation between carrier concentration and mobility: $\rho =1Ne\mu $. The carrier concentration and mobility are connected through the semi-empirical relation: $\mu (N)=\mu 0+\mu 11+NNref\gamma $. This model is based on the fact that, at low carrier concentration the electron mobility is dominated by phonon/lattice scattering. With higher carrier concentration comes more scattering: electron-electron, electron-impurity scattering.^{10,13} Electron and impurity concentration are inherently connected to each other. The impurities are essentially the defects and excess Bi present in the material, which act as dopants and hence increase the electron concentration.^{13} This increases the scattering of the carriers and therefore lowers the mobility. In our previous experiment (Sahu *et al.*),^{13} on this material, we obtained the numerical values for all the constants (*μ*_{0}, *μ*_{1}, *N*_{ref}, *γ*). Here *μ*_{0} (∼ 6.33 x 10^{-4} m^{2}/(V s)) is the lower limit of the mobility for a heavily doped channel where impurity and e-e scattering is dominant. The value *μ*_{1} is 9.9 x 10^{-4} m^{2}/(V s) and *μ*_{0} + *μ*_{1} is the upper limit of the mobility of electrons of an undoped film, where the scattering is minimal and mostly dominated by phonon/lattice scatterings. *N*_{ref} is the reference carrier density (∼ 3.9 × 10^{26}/m^{3}), which corresponds to the carrier concentration that gives a mobility of half way between the two extremes (heavily doped and undoped cases). And the exponent γ is 3.1, which denotes the rate at which mobility changes from maximum to minimum value. It is also worth pointing out that, these constants might be dependent on the intrinsic material properties (stoichiometric ratio, grain sizes etc.), which give rise to various scattering processes. Combining the two relations, we end up with:

Based on Equation (1), we can calculate the carrier concentration and carrier mobility. Fig. 1 shows the sheet carrier density (*N*_{S}=*N* x *film thickness*) for different gate voltages. One of the key things to notice for gate voltage dependence is the symmetry at left and right gate voltage of resistivity during forward and backward scans. It would be reasonable to assume that the transport mechanism of the film during electron accumulation and depletion should be relatively similar. Hence, we can use Equation (1) for both accumulation and depletion mode operation. Based on the calculated sheet carrier density, we can obtain the total capacitance. The total carrier density is a sum of bulk carriers and accumulated/depleted charges:

where Δ*N*_{S} is the sheet carrier density from accumulated/depletion of charges and *N*_{B} is the bulk carrier density. The bulk carrier density is constant, given that the gate voltage does not affect the bulk, which is a consequence of small Debye length (∼ 5 Å, using Equation (4)). The total capacitance is given by:

This capacitance is plotted in Fig. 3(a, b). As highlighted in Fig. 2(b), this total capacitance is a series of two capacitances: gate capacitance (*C*_{g}) and the channel capacitance (*C*_{c}) coming from the charge decay, due to screening, in the bulk of Bi_{x}Se_{1-x}. Gate capacitance is due to the accumulation of charges at the top interface (Bi_{x}Se_{1-x}/SiO_{2}). Channel capacitance is due to the decay of charge concentration as we move away from the top interface and into the bulk of Bi_{x}Se_{1-x}. This can also be depicted as the thickness of the accumulated charge at Bi_{x}Se_{1-x}/SiO_{2} interface, which is given by Debye length of Bi_{x}Se_{1-x}. Hence, the channel capacitance is given by:^{19} $Cc=\u03f5cLD$. Here *ϵ*_{c} is the dielectric constant of Bismuth Selenide (assumed to be ∼ 100 *ϵ*_{0}, based on previous reports^{15,17,18}) and *L*_{D} is the Debye length, which can be calculated using:

Fig. 3(c, d) shows the hysteretic behavior of *C*_{c}. One of the key observations is that *C*_{c} (units in pF/μm^{2}) is much greater than *C*_{t} (units in fF/μm^{2}). Being a series combination $1Ct=1Cg+1Cc$, the contribution of channel capacitance (C_{c}) to the total capacitance (C_{t}) will be small (C_{t} ∼ C_{g}). The capacitances give us the rate of change of charge density with respect to gate voltage. The backward scan (red) of *C*_{t} shows a peak and sudden decrease around V_{g} = -7V. We call this the critical voltage (V_{gc}). This behavior is in fact repeated in the second device (from Paper I, Sahu *et al.*)^{14} as well. For a given parameter X (V_{g}), we have forward and backward scan of the parameter (X_{f} (V_{g}) and X_{b} (V_{g})). The sum (X_{a} (V_{g})) and the differential (X_{d} (V_{g})) values of the parameters can be written as: X_{a} (V_{g}) = X_{f} (V_{g}) + X_{b} (V_{g}))/2 and X_{d} (V_{g}) = X_{f} (V_{g}) - X_{b} (V_{g}))/2. These sum and differential values of parameters allow us to examine the symmetry of the parameter at positive and negative gate voltage more clearly.

## DISCUSSION

Fig. 1(a, b) shows the change in sheet carrier density with respect to gate voltage. As expected, this shows a hysteretic behavior. The sheet carrier density increases at positive gate voltage due to accumulation of electrons in the “n-type” Bismuth Selenide. At negative gate voltage, the sheet carrier density decreases with gate voltage due to electron depletion. Fig. 1(c, d) shows the change in carrier mobility with respect to gate voltage. The mobility shows the exact opposite behavior of the carrier density. This is due to additional scattering processes at higher concentration, which decreases mobility (Equation (1)). The sum and differential values show a region of stability at lower gate voltage magnitude (saturated region).

The leakage current is directly measured as a function of gate voltage. Fig. 2(c, d) shows the change in gate resistance (R_{g} = dV_{g}/dI_{L}) with respect to gate voltage. The gate leakage current (I_{L}) is in the range of 10^{-9} – 10^{-10} A, which is much smaller than the 10μA (drain current). Our calculations suggest that the change in voltage, during FET device operation cannot be accounted for by leakage current, which will lead to miniscule changes. Hence, the changes in resistivity and carrier concentrations are almost entirely due to accumulation of charges at the top interface. The gate RC time constant ranges from 1.5 to 150 msec, which would correspond to quasistatic capacitance as our gate voltage ramp time (∼ 1 s) is much greater than the RC time constant.

Fig. 3(a) shows the change in total capacitance with respect to gate voltage. This total capacitance shows a negative value within the saturated region of charge trapping. This is due to the increase in carrier density even under decreasing gate voltage. This can happen when some carriers tunnel into the shallow traps in the dielectric layer even under a low magnitude electric field, probably close to the interfaces. We start by understanding the forces behind the changes in capacitance. We identify two key factors behind the change in gate capacitance: (1) The level of electron trapping/detrapping in gate dielectric (2) Density of states due to Fermi level movement.

We start by looking at the first point. As we increase the magnitude of the positive gate voltage, the level of hole trapping in the gate dielectric will also increase, which will cause the level of electron trapping in the channel to go up and hence the capacitance. Similarly, during negative gate voltage, the level of electron trapping in the gate dielectric will increase, resulting in an increased hole concentration in Bi_{x}Se_{1-x} and thus resulting in higher capacitance. Hence, the level of electron trapping/detrapping in the gate dielectric will always tend to favor the direction of change. This means that the electron/hole trapping will always increase the capacitance as we increase the magnitude of gate voltage, as seen from Fig. 3(a, b).

Next we look at the effects of changes in density of states. At positive gate voltages, we achieve electron accumulation in the channel, which results in a higher Fermi level in conduction band. This would result in an increase of the density of states at positive gate voltages. This change could be exponential near the conduction band edge. This increase in density of states will add to the level of change of electron concentration in the channel and hence will add to the increase in capacitance. Similarly, electron depletion at negative gate voltage will result in a lower Fermi level (towards the bulk band gap) and a decreased density of states. This will move the Fermi level closer to the Dirac cone and the bulk band gap. This will lead to a lower level of change of carriers in the channel and hence lower capacitance. So, at negative gate voltage, we have a conflict between the change in capacitance from carrier trapping and density of states. The carrier trapping will tend to enhance the capacitance whereas the density of states will tend to decrease the capacitance. This kind of opposing driving forces results in the peaking of the capacitance at some point at negative gate voltage. Hence we believe that at V_{g} > V_{gc}, the capacitance is driven by carrier trapping. However, at V_{g} < V_{gc} the changes due to density of states take over and we see a reduction in capacitance. At V_{g} ∼ V_{gc}, we enter a region of very low density of states (conduction band edge). We know that in TIs the density of states changes sharply in the Dirac cone, with minima at the Dirac point. There is also a good possibility that the Fermi level has entered the Dirac cone (bulk band gap), resulting in a sudden decrease in density of states. It should be noted that the conduction band edge and the beginning of Dirac cone could be indistinguishable in polycrystalline films. In polycrystalline films, the quantum confinement effect can blur out the continuous Dirac cone and replace it with discrete states with lower density of states as we move towards the bulk band gap.^{12}

One of the key parts about using such a charge trapping gate layer is the ability to pin the Fermi level using gate dielectric carrier traps. This would allow one to ensure that the Fermi level always stays fixed at a certain point, as long as the operating gate voltage is below the energy depth of the traps. Applying a gate voltage higher than the energy depth of the traps will result in changes in the trap density and will create a different pinning level. This pinning can be used to determine the initial state of the Fermi level (V_{g} = 0). Furthermore, this movement of Fermi level can also be used to manipulate the topological states that contribute to the conduction process. When the Fermi level is in the conduction band the spin-momentum locked states, arising from being in a dispersive regime, contribute to the surface conduction.^{12} However, as the Fermi level moves closer to the Dirac cone/bulk band gap, the surface conduction can be dominated by traditional topologically protected surface states.

## CONCLUSIONS

In summary, we analyzed the transport behavior and physics of FET devices in detail. We analyzed the carrier concentration and mobility, which show hysteresis due to charge trapping. We also calculated the gate capacitance and channel capacitance. We discussed the various driving forces resulting in changes to the capacitance with respect to gate voltage. We characterized the properties of conduction band edge by identifying the critical gate voltage. This allowed us to understand the effects of gate traps on the transport properties of sputtered topological insulator. The charge-trapping gate can be used as a surface Fermi level pinning technique in topological insulators.

This work was in part supported by ASCENT, one of the six centers of JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA. Portions of this work were conducted in the Minnesota Nano Center, which is supported by the National Science Foundation through the National Nano Coordinated Infrastructure Network (NNCI) under Award Number ECCS-1542202. Parts of this work were carried out at Characterization facility, University of Minnesota, which receives partial support from NSF through the MRSEC program, under Award Number DMR-1420013.

## DATA AVAILABILITY

The data that support the findings of this study are available from the corresponding author upon reasonable request.