Investigation of a novel solid-state dual meander pulse-forming line with 10 kV-class withstand voltage Open Access

Pulsed power technology is involved in numerous applications in fields such as high-power microwaves,¹ bioelectronics,² medical treatment,³ environmental protection,⁴ and food processing.⁵ Structure miniaturization and dielectric environmental tolerance have become increasingly critical in the current design and manufacturing process, especially for long life-time pulsed power systems.^6,7 The pulse-forming line (PFL) is one of the key components in pulsed power systems. It serves as an intermediate stage that is charged to hundreds of kilovolts in a few microseconds and then discharged to the load, generating a high-power pulse with tens to hundreds of nanoseconds.⁸ Presently, conventional liquid dielectrics as a PFL energy storage medium cannot meet the requirements for system compactness and portability because they will either freeze at low temperatures (like water) or have low relative permittivity (like transformer oil).

Compared with liquid dielectrics, explorations on solid-state dielectrics seem more interesting for compact, portable pulsed power systems.⁹ In particular, ceramic has become a desirable candidate with both high energy storage density and good environmental tolerance because of its superior characteristics including high dielectric constant and high breakdown field.^10–12 However, there remain several extraordinary challenges for its extensive use in systems. First, large size brings lower energy storage density.¹³ It is because the dielectric breakdown strength will decrease with an increasing size such as thickness, especially in the mm to cm range. Besides, difficulties still exist in large scale ceramic manufacturing.¹⁴ Hence, the ceramic pulse-forming module is usually produced in smaller thickness to withstand tens of kilovolts in practice.^15,16 Then, a pulse-forming network (PFN) consists of identical, separate inductors, and capacitors are employed,^17,18 which can generate several hundred kilovolt pulses with a certain pulse duration.

In principle, a one-stage PFN suffers from limited output voltage determined by the insulation strength of a single ceramic capacitor. To maximize the output voltage, the capacitors can be stacked in series, and thus, the PFN-Marx configuration for multiple stages is proposed.^17,19 It can adjust electrical parameters of output pulses but also brings unexpected self-inductance, which influences the rise time and quality of a long output pulse. In addition, the space utilization is inefficient since a heavy insulating encapsulation is needed for each capacitor and extra insulating distance for LC-units is necessary. Therefore, solid-state PFL design should be more advantageous relative to PFNs.

Currently, the planar structure is more realistic for solid-state pulse-forming modules due to its fabrication simplicity. Indeed, it can be achieved conveniently with a mature 2D electrode technology.²⁰ In printed circuit boards (PCBs), the meander is commonly used as the delay lines to form pulse delay between two points or devices with little board space lost.²¹ In this regard, the meander pulse-forming line (MPFL) as one periodic structure can produce a longer pulse duration with satisfactory dispersion and broadband while the module size decreases.²² However, the defect is that fringing electric field enhancement near the two terminals in the MPFL reduces largely its practical breakdown voltage,²³ which is urged to be improved for its full potential realization.

In this paper, we extend the previous work and propose a novel solid-state dual meander pulse-forming line (DMPFL) with an improved electrode structure. Such a structure enables the fringing electric field to be more evenly distributed, further improving the withstand voltage. In Sec. II, structure design is described. In Sec. III, dispersion analysis of the DMPFL is carried out. In Sec. IV, simulation investigation of time delay and pulse-forming with computer simulation technology (CST) simulation is presented. In Sec. V, experiments on the withstand voltage of the DMPFL are conducted to verify its actual performance; then, double-line pulse superposition of DMPFLs is realized; in addition, a solid-state Blumlein module based on the DMPFL and photoconductive semiconductor switch (PCSS) is introduced and tested. Finally, a brief conclusion is given in Sec. VI.

The structure of the DMPFL is as shown in Fig. 1. It is finished from a PbO–BaO–Na₂O–SiO₂–Nb₂O₅, 250 × 90 mm², 4 mm thick, glass-ceramic substrate with the dielectric constant of about 225. One side of the substrate is covered by a conductor solid layer, which plays the role of shielding electrode, defined as the shield electrode, while the meander line structure with a parallel conductor array, defined as the meander electrode, is on the other side. The line width and separation of the meander electrode are 5 mm and 4 mm, respectively. The connection points of the DMPFL are located at the midpoint on both sides. With slip casting techniques,²⁰ the ceramic phase is closely wrapped by the glass phase, thus providing ceramic bulk with both high dielectric constant and high breakdown strength.

Simply, the DMPFL can be regarded as two MPFLs connected in parallel. By fabricating two MPFLs with the same start area and the end area on the same substrate, the break area where the maximum field enhancement usually exists and then causes electrical breakdown can be eliminated in geometry. The connected two MPFLs on the same substrate both charge and discharge in parallel with the same potential, fundamentally different from the method of two lines discharging in series in the Blumlein line. Furthermore, this layout can half the inductance compared with the MPFL.

In the field of pulsed power technology, it is common to make system components correspond with circuit elements for intuitive evaluation. According to the transmission line theory, one can obtain the equivalent circuit of DMPFL, as shown in Fig. 2. Its periodicity in the z-direction is similar to that of the MPFL as they are both periodic systems composed of double conductors. In the z-direction, the transmission system is symmetric with the axis x = 0 due to the uniformly symmetric structure of the DMPFL.

First, we consider half of the DMPFL (x > 0). As a two-stage periodic system, the voltage V_m and current I_m on the mth (m = 1, 2, …) band can be expressed by

where k is the angular wave number, ϕ is the phase shift of two adjacent conductors, A₁, A₂, B₁, and B₂ are constant coefficients, and Z is the characteristic impedance of the multi-parallel conductor system. The boundary conditions at the end of the DMPFL are

For x < 0, the voltage and current on the mth band can be expressed as Eq. (1) in terms of the structural symmetry. Here, the boundary conditions are

Combining Eqs. (2) and (3), the boundary condition of current can be reasonably set as

Then, the boundary conditions can be unified as

Consequently, one can obtain the dispersion relation based on Eqs. (1) and (5). Specifically, frequency characteristics of the two electromagnetic parameters, characteristic impedance Z and electric length τ₀ (half of the pulse width τ), of the DMPFL can be presented by combining the structure dimensions with the above calculation. For simplicity, we can also assume that the DMPFL is equivalent to two independent MPFLs in parallel and then calculate parameters using the theoretical model of MPFL.²² The calculated characteristic impedance and electric length are 3.75 Ω and 41.2 ns, respectively. It is indicated that the DMPFL can output a pulse up to 80 ns width. Moreover, the parameters have little change in the frequency range [0, 1/τ] of the output electric pulses according to the calculation, which proves it possesses a good capability to form quasi-square wave pulses.

In order to validate the dispersion analysis of the DMPFL, CST Microwave Studio (MWS) is used to simulate the transmission characteristics of traveling waves. With the similar idea in Ref. 23, we regard the pulse-forming line as a transmission line to obtain the characteristic impedance and electric length. The schematic diagram of ports is presented in Fig. 3(a). Port 1 serves as the exciting port, into which an 80 ns width, 1 V amplitude, quasi-square voltage pulse (20 ns rise/fall time, 60 ns flat-top) is inputted. Port 2 is the port to absorb the transmitted voltage pulse, of which the impedance is set to 3.75 Ω (the same as the calculated Z). The voltages of both ports are monitored in CST. Figure 3(b) shows the comparison of simulated input and output waveforms. It can be seen that the flat-top amplitude of the received signal is close to that of the source signal. The delay time between the two signals is about 40 ns, which fits well with the calculated τ₀. Hence, the delay time simulation is consistent with the dispersion analysis.

As the pulse-forming simulation of the single DMPFL is straightforward, here we carried out the formation of two stacked DMPFLs (double-line or Blumlein line). Naturally, there exist different stacking ways for two DMPFLs. We define the meander electrode as side A, the shield electrode as side B, and the distance between the two DMPFLs as D. If they are stacked in a way that meander electrodes (A-sides) rather than shield electrodes (B-sides) face each other, the stacking mode is defined as BAAB, as shown in Fig. 4(b); otherwise, it is ABAB. As the DMPFL is not totally shielded by a conductor shell, the electromagnetic coupling (mainly referred to as capacitive coupling) happens when they are stacked, and the coupling could affect the voltage multiplication and energy efficiency.²⁴ Therefore, it should be analyzed in the simulation. We did two simulations with CST to analyze the pulse-forming characteristics: the field-circuit co-simulation method and the transient analysis with the impulse response method.

Figure 4(a) shows the circuit principle diagram of the field-circuit co-simulation. The two DMPFLs are charged in parallel by a voltage source E₁; then at 800 ns, the switch S is triggered by the voltage source E₂, and it shorts one DMPFL through ports 1 and 1′. The matched resistor (7.5 Ω) is put between ports 2 and 2′. The two DMPFLs are connected with the line between ports 3 and 3′. The corresponding current waveform is measured, as shown in Fig. 4(c). It can be observed that the output pulse width is about 82 ns; therefore, 7.5 Ω load resistance matches the Blumlein line well. However, such field-circuit co-simulation consumes long time, which is not conducive to carrying out multi-group simulations of DMPFLs for comparative analysis. One more concise equivalent model is needed.

Figure 4(b) indicates the transient analysis of the equivalent wave process of the DMPFL-based Blumlein line. Three ports are introduced in the model, of which the functions are as follows: Port 1 is the discrete voltage port, where a fast rising/falling voltage pulse signal with the width t₀ that is at least three times longer than the electric length τ of the DMPFL is fed. Port 2 is the discrete port of resistance (7.5 Ω), consistent with the load resistance. Port 3 is the discrete port of resistance (0.01 Ω), serving as a short-circuit boundary. The simulated process can be divided into four stages as follows.

First, 0–τ, the pulse voltage signal is fed into port 1 and then transmitted from left to right along the upper DMPFL, while the measured voltage at port 2 is still zero.

Second, τ–3τ, the signal has reached port 2 and then is being transmitted into the bottom DMPFL from right to left, until the leftmost port, where full reflection occurs. The signal reflected by the bottom DMPFL has not yet been transmitted to port 2. With the voltage transmission formula, the voltage expression at port 2 accords with that of output voltage as port 2 resistance and the bottom DMPFL characteristic impedance are in series.

Third, 3τ–t₀, the reflected signal has reached port 2, while the signal coming from the upper DMPFL is transmitted there continuously. In terms of wave calculation, there is no voltage difference between them at port 2. If t₀ is long enough, both the upper and bottom DMPFLs can be considered fully charged after this stage.

The inverse process during the first three stages is exactly a discharge process of a fully charged Blumlein line. On this basis, we can obtain the output pulse voltage by detecting the voltage of the matched load at port 2, similar to that in stage 2.

Fourth, after t₀, after the input voltage at port 1 returns to zero, we can continue acquiring the output voltage waveform with the same measurement method since this pulse-forming stage still follows the principle of the Blumlein line.

Through the four stages, the typical waveforms (voltage at ports 1 and 2) of the single-stage Blumlein line are shown in Fig. 5. The amplitude of the quasi-square wave voltage signal fed into port 1 is 1 V, and the pulse width is 380 ns. The rise time from 0 V to 1 V is 10 ns, equal to the rise time from 1 V to 0 V. The port 2 waveform has two pulses, of which the pulse widths are both 81 ns, about twice the delay time between the two signals. The voltage amplitude in the port 2 waveform is 1 V so that the load resistance matches the impedance of the DMPFL.

Furthermore, under different placement modes (BAAB, ABAB) and distances (D = 25 mm, 10 mm), pulse-forming characteristics of the DMPFL-based Blumlein line are simulated, and the pulse voltage waveforms obtained at port 2 are shown in Fig. 6. The three waveforms basically overlap, except that in the BAAB type placement with D = 10 mm, of which the pulse width is stretched and the amplitude decreases. The results indicate that the A-side electrode (meander electrode) cannot weaken electromagnetic coupling between the two DMPFLs, especially when placed close to each other. For ABAB type, however, the voltage pulse varies little though D decreases, as the B-side electrode (shield electrode) nearly covers the dielectric plate, which is beneficial to electromagnetic shielding. In the case that the electromagnetic coupling between two lines reduces the voltage superposition efficiency, we adopt ABAB type in the subsequent design of DMPFLs.

Three tests were carried out, namely, the withstand voltage, double-line pulse-forming, and the integration of a DMPFL-based Blumlein line with the PCSS. The results are all from representative samples, and the uncertainty of experimental instruments is 5%.

One of the primary goals of the designed DMPFL as mentioned is to obtain a higher withstand voltage compared with that of the MPFL by optimizing electric field distribution near the dielectric corner and the ends in terms of the symmetrical structure. So, we should carry out withstand voltage tests to investigate this regard.

Figure 7(a) shows the test setup of the withstand voltage. The primary capacitor (C, 20 µF) is charged by the primary energy supply to a certain voltage. Then, the thyristor switch S is triggered and a high voltage pulse (∼10 kV) is applied on the MPFL or DMPFL under the action of the transformer (ratio 1:20). The voltage waveforms are measured with the ceramic resistance voltage divider (2 kΩ:1 Ω). All measurement probes are calibrated, and we estimate the measurement error to be less than 5%.

Figure 7(b) shows four typical pulse voltage waveforms of the DMPFL sample. The sample suffers no electrical breakdown in the three tests at lower peak voltages until the pulse voltage is up to 32 kV (black line). Figure 7(c) shows the typical voltage waveforms of the MPFL in the same experimental conditions. It also includes the waveforms without breakdown at lower peak voltages, and the breakdown occurs as the voltage is about 22 kV. Therefore, the DMPFL can maintain a significantly higher operating voltage than the MPFL. Specifically, the failure location for the MPFL seems regular, while it varies between devices in the DMPFL, which indicates that the MPFL fails due to the structure limitation, while the DMPFL fails due to limitation of the materials, in line with the expectation of the structural design of the DMPFL.

Figure 8 shows the typical photos of the glass-ceramic MPFL²³ and DMPFL after breakdown for comparison. It can be found that the location of the breakdown point is not distributed in the possible positions for the MPFL (usually the corner area and the break area), but a more random position. This phenomenon also indicates that the design for electric field distribution works effectively, leading to the results in Fig. 7(b).

On the basis of simulation, a circuit, as shown in Fig. 9, is set up, and the double-line pulse superposition tests with the form of a single-stage Blumlein line are developed. The system consists of a primary energy supply, a primary capacitor (C₁), a pulse transformer (L_p and L_s), a thyristor switch (S₁), a load, and a DMPFL. The DMPFL stacking belongs to ABAB type. The load resistance is 7.5 Ω. The self-breakdown gap switch can break down under various charging voltages by adjusting its gap. The voltage waveforms are measured with a 2 kΩ:1 Ω ceramic resistance voltage divider.

Figure 10 demonstrates the measured voltage waveforms at the charging voltage of 6 kV, where the two voltage channels, V₁ on the DMPFL and V₂ on the load, are monitored. One can find that the delay time between V₁ and V₂ is about 42 ns and the pulse width of V₂ is 84 ns; thus, the former is nearly half of the latter. Therefore, the experimental results accord with the typical characteristics of the Blumlein line.

The PCSS is promising in the field of power superposition for several advantages.^25–27 First, it offers compactness, high repetition frequency, and low on-resistance as a solid-state switch. Second, it allows multiple outputs of the high-voltage pulse with a synchronous time of the sub-nanosecond level. Third, its operation can be controlled by a nanosecond laser with only microjoule level pulse energy. Fourth, it achieves optical isolation, and thus, there is no electromagnetic interference. Finally, it possesses a planar structure similar to that of Blumlein lines, which is easy to be integrated. Nowadays, GaAs PCSSs are of particular interest due to their nonlinear mode with fast response and high gain.^28,29 In consequence, we try to apply the GaAs PCSS to the DMPFL-based Blumlein line to explore the solid-state modules for power superposition.

Figure 11 gives the experimental circuit of the Blumlein line based on the GaAs PCSS and DMPFL. The semi-insulating GaAs PCSS comprises a 5 mm switching gap, fabricated on a 14 × 6 mm², 600 µm thick substrate, with the dark resistivity of up to 5 × 10⁷ Ω cm. The nonlinear GaAs PCSS is in high gain mode, illuminated by a 905 nm laser (20 ns FWHM, ∼306 µJ pulse energy) from an LD trigger. A Stanford DG535 digital delay generator is used to generate three standard pulses with fixed delay. The first signal is to control the conduction of the thyristor S₁ and make the pulse charger output a pulse of microsecond rise time. Next, the second signal is to trigger the LD driver to produce the light pulse and then trigger the PCSS near the peak of the output voltage. Then, the third signal is directly detected by a 600 MHz bandwidth oscilloscope as a reference signal. The DMPFL stacking is of ABAB type as before, and the load resistance is 7.5 Ω.

The voltages on the DMPFL (V₁) and load (V₂) are monitored as the GaAs PCSS is turned on under voltages of 4 kV, 7 kV, and 11 kV, respectively, as shown in Fig. 12. It is noticeable that the waveform of V₂ in Fig. 12 means a more standard quasi-square wave than that in Fig. 10. The waveform of V₁ in Fig. 12 follows basically that in Fig. 10 using the self-breakdown gap switch, whereas the former is smoother. The flat-top unevenness in Fig. 10 results from the oscillation generated by the switch as breakdown happens, which is weaker in the PCSS. In Fig. 12, the amplitude of V₁ is much lower than that of V₂ with a difference of about 3 kV. This is because the characteristic impedance of the designed DMPFL is 3.5 Ω, and thus, a higher electric field is required (1.5 kV–2.5 kV) for the nonlinear GaAs PCSS to maintain high current conduction.

The PCSS on-resistances R_on are calculated as 8 Ω at 4.3 kV, 2.7 Ω at 6.6 kV, and 1.4 Ω at 11.3 kV with

where V_1min is the minimum value of the charging voltage and V_2max is the peak value of the output pulse.

Furthermore, the switch lifetime of the GaAs PCSS is dozens of pulses under 11 kV charging voltage since the current through the nonlinear PCSS can be up to kA levels due to the low on-resistance, and constricted in filaments. Consequently, the excessive current density limits switch lifetime. To improve this, the following measures can be effective: (1) electrode design can adopt the interdigital structure to form multiple channels as light shines on the PCSS, increasing the operating current; (2) one can treat the illuminated surface as a groove structure to induce the generation of multiple filaments; (3) the spot can be optimized to facilitate the channel formation.

A novel solid-state, glass-ceramic DMPFL with high withstand voltage aiming to satisfy the compactness and reliability demands of long life-time pulsed power systems is investigated with theory analysis, simulation, and test experiments: (1) the DMPFL can complete the homogenization of electric field distribution, thus substantially improving the withstand voltage to 32 kV compared with that of the initial MPFL structure; (2) for double DMPFL superposition, an 83 ns quasi-square wave pulse with the 20 kV voltage amplitude is obtained on a 7.5 Ω load; (3) the back shield electrode is beneficial to electromagnetic shielding and thus should be used in the design; and (4) the PCSS in combination with the DMPFL can produce output pulses with better properties than the self-breakdown spark gap switch. These results manifest that it could be expected to be extensively applied in the next generation of solid-state Blumlein modules.

Y.Z. and L.W. contributed equally to this work.

The data that support the findings of this study are available from the corresponding author upon reasonable request.