Interface trap and border trap characterization for Al₂O₃/GeO_x/Ge gate stacks and influence of these traps on mobility of Ge p-MOSFET

Germanium (Ge) is one of the candidate materials for the next generation metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) due to its high carrier mobility and high compatibility with the silicon (Si) platform.^1,2 Besides, the quasi-direct bandgap of Ge can make a possibility for near infrared optical applications such as on-chip optical interconnect.^3,4 Other Ge-based novel devices such as spintronics⁵ and thin-film transistors^6,7 are also attracting great attention. Even though Ge has many advantages, there are many issues such as the leakage current in bulk Ge and the low dopant solubility of Ge. In order to suppress the leakage current and integrate Ge devices with the conventional Si process, the Ge-on-insulator (GOI) technology^8–11 is developed. To increase the active dopant concentration, the epitaxial growth of in situ doped Ge is also studied.^12,13

In order to bring out the high potential of Ge, the formation of high quality dielectric films on Ge as a gate insulator and passivation layer is necessary. Particularly, the quality of the gate insulator directly affects the current drivability of Ge MOSFETs or Ge spin MOSFETs. Many research groups have focused on the fabrication of Ge gate stacks and developed the characterization method of its interface state. About fabrication, nowadays, it is well known that GeO_x/Ge has good interfacial quality.^14,15 Therefore, Ge gate stacks with a thin Ge oxide interlayer, such as SiO₂/GeO₂¹⁶ and Al₂O₃/GeO_x,^17,18 have been studied actively. About characterization, a low temperature conductance method¹⁹ and deep level transient spectroscopy (DLTS)²⁰ are widely used for the quantitative evaluation of interface traps (ITs). On the other hand, in the case of the Ge MOS, not only ITs but border traps (BTs) located in a gate dielectric are also problematic because these traps degrade MOS characteristics and mobility. For deep understanding and performance improvement of the Ge MOS device, both the density and the spatial position of BTs in a stacked gate dielectric should be clarified. However, an in-depth study about BTs in a Ge stacked gate dielectric is limited.²¹ Recently, we succeeded in separating BT and IT signals through the DLTS measurement for SiO₂/GeO₂/Ge gate stacks grown by thermal and plasma oxidation.²² 

In this study, the densities of ITs (D_it) and BTs (N_bt) in Al₂O₃/GeO_x/p-Ge gate stacks grown by post-plasma oxidation (PPO) were evaluated. In addition, to study the relationship between BTs and the mobility of devices, Ge p-MOSFETs with Al₂O₃/GeO_x/Ge gate stacks were also fabricated and analyzed.

In Sec. II, the fabrication procedures of MOS capacitors and MOSFETs are described. In Sec. III, the structural analyses and electrical properties of Al₂O₃/GeO_x/Ge gate stacks are investigated. The electrical properties of Ge p-MOSFETs with the same gate stacks are also reported. In Sec. IV, the origin of the flat band voltage (V_FB) shift and position of BTs are discussed. The effect of BTs on the mobility of MOSFETs is also discussed. Section V presents the conclusions.

The fabrication process of MOS capacitors is as follows. The p-type (100) Ge substrate with a doping concentration of 2.3 × 10¹⁶ cm⁻³ was used. After chemical cleaning by acetone and HF solution, the first layer of Al₂O₃ was deposited at 300 °C by atomic layer deposition (ALD) with precursors of water and trimethylaluminum for 3, 9, 14, and 20 cycles, corresponding to four samples, followed by PPO using electron cyclotron resonance (ECR) at room temperature with a microwave power of 500 W and Ar/O₂ flow rates of 18/3 sccm for 1 min. The second layer of Al₂O₃ was deposited at 300 °C by ALD for 25 cycles to avoid current leakage during electrical measurements. For comparison, one sample with 45 cycles of Al₂O₃ deposition by ALD without PPO was also fabricated. 400 °C post-deposition annealing (PDA) was performed for 30 min. Then, the TiN layer was deposited by sputtering, followed by 350 °C post-metallization annealing (PMA) for 20 min. After that, the Al layer was also deposited and the gate electrode was patterned by lithography. To improve the electrical contact between TiN and Al layers, contact annealing (CA) was performed at 300 °C for 10 min. Finally, an InGa back contact was formed. All annealing in this study was performed in N₂ ambient.

Ge p-MOSFETs were fabricated on an n-type (100) Ge substrate with a doping concentration of 9.3 × 10¹⁵ cm⁻³. We used a gate-first process. Both the process flow and the device structure are shown in Fig. 1. After wafer cleaning, SiO₂ field oxide was deposited by ECR sputtering for isolation. Then, windows were opened by standard lithography and wet etching to define the active areas. To eliminate the influences of sputtering and etching on the surface of the active area, sacrificial GeO₂ was formed by thermal oxidation at 450 °C for 30 min in O₂ ambient and removed by rinsing in a dilute HF solution. Next, an Al₂O₃/GeO_x/Ge gate stack was fabricated by the same method as MOS capacitors, as mentioned above. After 400 °C PDA, the Al/TiN gate electrode was deposited and patterned. To form the source/drain (S/D), B ion implantation was carried out with an acceleration energy of 30 keV and a dose of 10¹⁵ cm⁻². The Al/Pt contact electrode for S/D was formed by the lift-off method, followed by CA and activation annealing (for S/D) at 300 °C for 10 min in N₂ ambient. Subsequently, an InGa back contact was formed. The active hole density of 4.3 × 10¹⁹ cm⁻³ was confirmed by Hall effect measurement. Both D_it and N_bt were characterized using DLTS.²² 

To clarify the formation of the GeO_x interlayer, x-ray photoelectron spectroscopy (XPS) measurement was carried out. Figure 2 shows the Ge 3d XPS spectra of Ge gate stacks with and without PPO at a photoelectron take-off angle of 90°. The spectra were calibrated with a Ge 3d core level (29.3 eV) and normalized by the signal intensity of the Ge bulk. The Ge oxide signal intensity decreases with increasing cycle number of the first Al₂O₃ layer. Simultaneously, the Ge oxide peak shifts to the low-energy direction, indicating that there is a change in the stoichiometry of Ge and oxygen. In other words, the x in GeO_x becomes less than 2 with decreasing energy of the Ge oxide peak (the lower the energy, the smaller the x in GeO_x). The spectrum of the 20-cycle one is well overlapped with that of the one without oxidation.

The electrical properties of Al₂O₃/GeO_x/Ge gate stacks were examined by using MOS capacitors. Figure 3 shows the capacitance–voltage (C–V) curves of Al/TiN/Al₂O₃/GeO_x/Ge MOS capacitors with varied cycle numbers of the first Al₂O₃ layer deposition. With increasing cycle number, the V_FB shifts to the positive direction and a bit stretch-out and small bumps can be seen. However, for the MOS capacitor without PPO, V_FB is even more positive and the bump is bigger than the others. The thickness and equivalent oxide thickness (EOT) for each oxide layer is listed in Table I. Here, Al₂O₃ thickness was measured by ellipsometry. To calculate the EOT of each dielectric layer, permittivities of Al₂O₃ and GeO_x were assumed to be 8.47 and 5.7, respectively. With increasing cycle number of the first Al₂O₃ layer, the GeO_x layer becomes thinner. Figure 4 shows the energy distribution of D_it. In the region close to the midgap, lower D_it can be achieved by the thicker GeO_x layer. However, in the region close to the valence band, the thicker GeO_x gives higher D_it. Figure 5 shows the N_bt for all capacitors. The details of the measurement have been shown elsewhere.²² The highest and lowest N_bt were observed in the 9- and 20-cycle capacitors, respectively. The temperature dependence of N_bt is obvious for the 9-cycle capacitor.

Figure 6 shows drain current (I_D) vs drain voltage (V_D) characteristics of p-MOSFETs with the Al₂O₃/GeO_x/Ge gate stack. Here, the channel length (L) and width (W) are 120 μm and 390 µm, respectively. The p-MOSFETs with a higher cycle number of the first Al₂O₃ layer showed higher current drivability. Figure 7 shows I_D and source current (I_S) vs gate voltage (V_G) characteristics with V_D = −10 mV. High off-states I_Ds at positive V_Gs are caused by the drain/substrate leakage current.^23,24 Here, the threshold voltage (V_TH) was obtained from the x-axis interception of I_S/g_m^1/2 vs V_G plots, where g_m is the transconductance, and V_TH for each sample are indicated as solid circles in Fig. 7. V_TH shifts to the positive direction with increasing cycle number, which is consistent with the V_FB shift obtained in C–V characteristics. Figure 8 shows the mobility of p-MOSFETs calculated by the split C–V method. All p-MOSFETs showed similar peak mobility (170–200 cm²/V s) at a low inversion carrier density region. On the other hand, in the high inversion carrier density region, the mobility of the 20-cycle one is higher than that of the others, of which the reason will be discussed later.

Even though the Ge oxide signal was not detected by XPS for the 20-cycle one, the difference in C–V curves (Fig. 3) of 20-cycle and w/o PPO can be seen. Therefore, we believe that there is a Ge oxide layer in the 20-cycle one, or at least, the interface property was changed during PPO. A similar clue can be found in the D_it result and will be discussed in a later part.

The V_FB shift is found in Fig. 3 even though the EOTs for all MOS capacitors are nearly the same. This is considered as an effect of fixed charges in first Al₂O₃ or GeO_x. To clarify the density of fixed charges (Q_f), another set of MOS capacitors with varied cycles of second Al₂O₃ deposition were fabricated, while the cycle numbers of first Al₂O₃ deposition were fixed. Their V_FBs are plotted in Fig. 9. Since V_FB’s are linearly dependent on the EOT while the cycle numbers of first Al₂O₃ deposition were fixed, the second Al₂O₃ is free of volume charges within the detection limit.²⁵ V_FB is given by the following expression:

where Φ_MS is the work function difference between the metal gate electrode and semiconductor, $εSiO2$ is the dielectric constant of SiO₂, and $ε0$ is the permittivity in vacuum. Since the electrode material and substrate doping were not changed, Q_f can be derived from the slope of plots without the information of Φ_MS. The fitting of data with Eq. (1) revealed positive Q_f with a density of 8.2 × 10¹⁰ cm⁻² in the 9-cycle capacitor and negative Q_f with densities of 2.9 × 10¹² cm⁻² and 4.6 × 10¹² cm⁻² in the 14- and 20-cycle capacitors, respectively. It was reported that ALD-grown Al₂O₃ contributes the negative polarity of interface fixed charges,^26–28 while GeO₂ contributes the positive fixed charges.^14,29,30 Therefore, Q_f became more and more positive with decreasing cycle number of the first Al₂O₃ due to thicker GeO_x. Accordingly, V_FB shifted negatively when the GeO_x layer was formed, which coincides with the finding of Matsuoka et al.²⁸ 

It is plausible that the thinner GeO_x interlayer causes a higher D_it near the midgap. Many groups have reported similar findings.^16,31,32 According to the XPS result (Fig. 2), when the GeO_x interlayer is thinner, GeO_x is composed of a higher portion of suboxides due to the shift of the Ge oxide peak. This could imply an increase in imperfect Ge–O or Ge–Ge bonds at the interface, causing the increase in D_it. By contrast, the D_it near the valence band decreases with decreasing GeO_x thickness. This phenomenon is similar to the defect termination during Al post-metallization annealing reported previously.³³ The thinner the GeO_x interlayer, the higher the chance of Al oxide existence at the interface, thus decreasing the D_it near the valence band. Because the 20-cycle sample contains an ultrathin GeO_x interlayer, Al₂O₃ possibly exists at the GeO_x/Ge interface. Instead, to be more precise, the interface could be considered as a mixture of Al oxide and GeO_x, and this Al-bonded oxide acts as the defect terminator, as we have found in the previous work.³³ 

Based on our measuring condition of N_bt, detected BT signals originated from the position with a depth of 0.4 nm measured from the GeO₂/Ge interface when the tunneling barrier is the valence band offset (∼3.6 eV) at the interface.^22,34 According to the thickness of GeO_x in Table I, the detected BT position can be categorized into three cases, as shown in Fig. 10. Since the GeO_x thickness of the 3-cycle capacitor is over 0.4 nm, the detected BT signals are from GeO_x [Fig. 10(a)]. The GeO_x thickness of the 9-cycle capacitor is ∼0.4 nm, implying that the detected BT signals are from the Al₂O₃/GeO_x interface region [Fig. 10(b)]. The GeO_x thickness of 14-cycle and 20-cycle capacitors is less than 0.4 nm, indicating that the detected BT signals are from Al₂O₃ [Fig. 10(c)]. Here, the actual position of the detected BTs should be less than 0.4 nm when we consider the valence band offset (∼5.4 eV for Al₂O₃/Ge) of Al₂O₃/GeO_x.³⁵ Even if we take into account the GeO_x stoichiometry change, which may slightly reduce the band offset of GeO_x/Ge, the measuring position should be still in Al₂O₃. After matching the BT position with N_bt, N_bt in GeO_x (∼2 × 10¹⁸ cm⁻³) is higher than that in Al₂O₃ (6–9 × 10¹⁷ cm⁻³), and the highest N_bt is in the Al₂O₃/GeO_x interface region (∼1 × 10¹⁹ cm⁻³). The temperature dependence found in N_bt of the 9-cycle capacitor implies the thermal process involved, and this is another clue that the signals are from the interface.

The remarkable results of Ge p-MOSFETs are the effective mobility difference in the high-field region. The mobility degradation in the high-field region is usually considered as an effect of surface roughness scattering.³⁶ In this paper, a potential cause for the difference in surface roughness is the plasma oxidation process. In principle, plasma oxidation should have the greatest impact on the 3-cycle sample and an almost negligible impact on the 20-cycle sample by considering the different thicknesses of the first-Al₂O₃ layer and the formed GeO_x layer. In addition, since the 3-cycle sample shows lower mobility than the 20-cycle one in the high-field region, the 3-cycle sample is supposed to have a rougher interface of GeO_x/Ge. To confirm this, scanning transmission electron microscopy (STEM) analysis was performed. Figure 11 shows a STEM high-angle annular dark-field (HAADF) image of the Al/TiN/Al₂O₃/GeO_x/Ge gate stack with 3-cycle first-Al₂O₃ deposition. The rms roughness value of the interface of GeO_x/Ge is ∼0.2 nm, which is nearly the same level as a commercial Ge wafer surface (0.19 nm) measured by using an atomic force microscope (AFM), implying that the surface roughness may not be the factor of the mobility degradation in the high-field region. To reconfirm the interface roughness, we removed the oxide layers by using 0.5% HF solution and measured the surface roughness of two extreme cases, 3-cycle and 20-cycle, by using an AFM.² Figure 12 shows 1 × 1 µm² AFM images of the GeO_x/Ge interface. The rms roughness values of 3- and 20-cycle samples are 0.21 nm and 0.20 nm, respectively, which are entirely consistent with the STEM result. Since the formation of native oxide of Ge is layer-by-layer growth,³⁷ the morphology of the Ge surface can be copied to the surface of its native oxide. Therefore, there is no doubt that these AFM measurements can provide the information of interface roughness. Consequently, the effect of surface roughness scattering cannot explain the mobility degradation in the high-field region.

Instead of surface roughness, BTs may be a relatively reasonable factor in this case. To discuss the connection between BTs and effective mobility, the band bending and trap states at different MOSFET operating conditions were considered. Figure 13 shows the band diagrams of Al₂O₃/GeO_x/Ge gate stacks at room temperature under weak inversion (ϕ_s = Ψ_B), strong inversion (approximately ϕ_s = Ψ_B + 0.23 eV in this case), and even stronger inversion (ϕ_s > Ψ_B + 0.5 E_g), where ϕ_s is the surface potential and Ψ_B is the energy difference of the Fermi level (E_F) and intrinsic Fermi level (E_i). It is worth noting that the charge neutrality level is ∼0.23 eV under the intrinsic Fermi level of Ge.³⁸ Under weak inversion [Fig. 13(a)], the acceptor-like ITs near the lower half of the bandgap showing negative charges cause mobility degradation. Under strong inversion [Fig. 13(b)], there is nearly no contribution of neutral charged ITs to mobility degradation. When the inversion gets even stronger [Fig. 13(c)], the donor-like ITs near the valence band showing positive charges cause mobility degradation. Besides, the BTs have a higher chance to capture holes (carriers) at this state due to the high electric field. Therefore, both ITs and BTs near the valence band cause mobility degradation in the high-field region. A similar finding about the effect of traps in the insulating oxide near the interface on mobility degradation in the high-field region was reported in a Si-based memory device study, even though the traps were not called BTs there.³⁹ 

The total effect of BTs in all Ge p-MOSFETs with Al₂O₃/ GeO_x/Ge gate stacks is categorized into two and summarized in Fig. 14. Since N_bt in Al₂O₃ is smaller than that in GeO_x or at the Al₂O₃/GeO_x interface, the 20-cycle gate with nearly no GeO_x contains fewer BTs in total compared to a 3- or 9-cycle gate. In addition, the 20-cycle gate shows the lowest D_it near the valence band, as shown in Fig. 4. Thus, in the high-field region, the highest effective mobility was achieved from MOSFETs with 20-cycle first Al₂O₃. Due to the low N_bt near the Ge valence band edge and the defect termination of the GeO_x/Ge interface, Al₂O₃ is an exceptional material for the gate dielectric of Ge p-MOSFETs.

By using DLTS, we evaluated D_it and N_bt of Al₂O₃/GeO_x/p-Ge gate stacks with different GeO_x thicknesses fabricated by PPO. By changing the thickness of GeO_x, we successfully measured N_bts in the GeO_x interlayer, the Al₂O₃/GeO_x interface region, and the Al₂O₃ layer, respectively. D_it near the midgap is lower in the MOS capacitors with a thicker GeO_x layer. By contrast, D_it near the valence band is lower in the MOS capacitors with a thinner GeO_x layer, owing to the defect termination by Al oxide. BTs are mainly located at the Al₂O₃/GeO_x interface region. ITs and BTs near the valence band edge of Ge affect the effective mobility of Ge p-MOSFETs in the high-field region. Therefore, reduction of ITs and BTs near the valence band is the key to reach high-performance p-MOSFETs. In this sense, Al₂O₃ is a suitable dielectric material for Ge p-MOSFETs.

The data that support the findings of this study are available within this article.

This work was partially supported by (JSPS) KAKENHI (Grant No. 17H03237 and 18KK0134) and the Advanced Graduate Program in Global Strategy for Green Asia, Kyushu University. XPS measurements were carried out using the facilities of the Center of Advanced Instrumental Analysis of Kyushu University. Ion implantation was carried out in the Center for Microelectronic System, Kyushu Institute of Technology.