Random telegraph signals caused by a single dopant in a metal–oxide–semiconductor field effect transistor at low temperature

The importance of atomic-scale features, such as a dopant^1–6 and a trap state,^7–13 has been widely recognized in the context of silicon (Si) quantum technology, such as nanoelectronic circuits,^{1–4,14–16} information processing,^{6–9,17–19} hardware security,¹² bio-sensing,¹³ and metrology.^{5,10,11,20,21} As the size of the Si metal–oxide–semiconductor (MOS) field-effect-transistors (FETs) approaches the physical limit, electronic circuits based on single-atom devices were proposed.^14,15 The use of solitary dopants as a fundamental building block of electronic circuits could be a disruptive solution to maintain the rate of device scaling.^{1–4,16,22,23} With regard to quantum information processing, spin qubits based on Si are considered to be promising due to their weak spin–orbit coupling and abundance of non-magnetic isotopes.^17–19 Realizing spin qubits with single-implanted donors is interesting as they can provide a discrete energy level with larger energy separation due to stronger quantum confinement than the one realized by a quantum dot (QD) defined by patterning or field-effect.⁶ Trap states in Si devices have been considered as an impediment to reliable performance of complementary-MOS (CMOS) FETs.^24–30 However, a few attempts have been made to perform single-spin manipulation based on trap states in a standard Metal–Oxide–Semiconductor Field-Effect-Transistor (MOSFET) for spin qubits, which proved to be successful.^7–9 In addition, the variation caused by trap states can be used as a fingerprint of a device for hardware security,¹² while a trap state in liquid-gated FETs for bio-sensing offers enhanced sensitivity to the change in the pH of the solution.¹³ Finally, such a trap state is known to be useful for a single-electron pump (SEP)^10,11 for quantum metrology.^20,21 SEP is a periodically driven single-electron transistor with tunable potential barriers, outputting a drain current of I_d = ef, where e is the elementary charge and f is the frequency at which the device is driven.^20,21 A SEP that takes the advantage of a trap state has achieved 7.4 GHz operation with an uncertainty of 20 parts-per-million (ppm),¹¹ approaching the metrological requirement of an electric current standard. Without doubt, engineering of such atomic-scale structures embedded in a Si device will continue to play a crucial part in future quantum applications.

The first challenge in utilizing atomic-scale features is to find their signatures in transport characteristics of the devices.^31–34 We have recently proposed the characterization of conventional Si MOSFETs with a long integration time at low temperature, which exhibits Coulomb diamonds (CDs)³¹ and random telegraph signals³² (RTSs) in current–voltage (I–V) characteristics. RTSs are discrete threshold voltage (V_th) variations over time,^25,35 and two V_th states are supposed to correspond to an empty and occupied state of a charge trap at the Si–SiO₂ interface or inside amorphous SiO₂.³² The physical origin of the CDs observed in the MOSFETs was, on the other hand, attributed to remote surface roughness of polycrystalline Si (poly-Si).³¹ In this sense, single-electron phenomena caused by trap states and structural disturbance in standard MOSFETs have been explored. However, toward application envisaging single-atom circuits^1–4,16 and spin qubits,⁶ the use of a single dopant is more desirable and suitable.

In order to achieve single-carrier manipulation using a solitary dopant in conventional MOSFETs, we focused on the dopants in the substrate, and the dopant ionization profile was electrically tuned in a systematic manner by applying reverse bias to the substrate. By doing this, we observed RTSs caused by trapping and detrapping of an electron by a donor in the substrate (well) of a p-type Si MOSFET at low temperatures. The device was initially characterized at 3.8 K while the substrate was grounded, and it showed a CD in I–V characteristics, indicating that the effective width of the channel is of the order of 10 nm. In addition, no RTSs were observed, which means that no trivial charge traps in the oxide or at the interface were present under this bias condition. However, RTSs started to be observed by applying positive bias to the substrate, which can be seen as discrete V_th shifts in I–V characteristics. Based on this observation, a physical model to explain this RTS based on trapping and detrapping of an electron by a donor was proposed, where the hole transport was significantly affected by the stochastic change in the depletion layer width depending on the charge state of the donor, the charge being neutral or ionized. The occupancy of the trap level and average lifetimes of two I_d states were systematically controlled by gate voltage (V_g), and the dependence of average RTS lifetimes on V_g suggests that the physical origin of the RTS could be different from trap states at the interface or in the gate oxide.^25,36,37 The temperature was gradually raised to 25 K in order to investigate the dependence of the RTSs on temperature, showing almost no dependence until 16 K before the faster RTS switching was observed at higher temperature. This indicates that the trapping and detrapping of an electron is achieved via quantum mechanical tunneling at low temperature.³⁸ 

This paper also quantitatively discusses the impact of applying reverse bias to the substrate onto the dopant ionization profile, based on the result of split capacitance–voltage (C–V) measurements with reverse substrate bias.^25,39 The application of the substrate voltage has been widely used in the context of Si quantum devices,^9,10,40 though the detailed study on its effect on carrier transport has not been performed. The width of the depletion layer was calculated as a function of V_g and voltage applied to the well (V_well), and the depletion layer was constantly extended as V_well increased, as expected. The effective hole mobility was also calculated as a function of the effective electric field,^24,41 and the degradation of hole mobility was prominent at a low effective electric field, where impurity Coulomb scattering is the dominant scattering mechanism. However, regardless of the values of V_well, the hole mobility approaches the universal mobility curve at a higher effective electric field, where Si–SiO₂ interface scattering dominates the mobility degradation.^24,41 This confirms that the primary effect of applying reverse bias to the substrate is to widen the depletion layer, rather than to increase the electric field across the MOS structure.^24,40

A p-type MOSFET fabricated using a standard 65 nm technology was characterized at various temperatures (from 300 K to 3.8 K) with a Janis pulse-tube refrigerator and a Keysight B1500 semiconductor parameter analyzer. Figures 1(a) and 1(b) show the schematics of the cross-sectional and birds-eye views of the device, respectively. The channel length (L) and width (W) were 50 nm and 10 μm, respectively, and the capacitive effective thickness (t_eff) is 2.4 nm. The device was mounted on and wire-bonded to a cryogenic sample holder, and the p-type handle layer was insulated from the holder by cryogenic varnish. Electrical contact to the n-type region in the substrate, well, was achieved from the dedicated pad connected to the well [Fig. 1(a)]. Phosphorous was used to form the well.

From our previous studies,^31,32 the presence of a QD was expected in our device, resulting in a narrower effective channel width than the actual dimension of the device [Fig. 1(b)]. Figure 1(c) shows the transfer characteristics [drain current (I_d) against gate voltage (V_g)] of the device at both 300 K and 3.8 K when the drain voltage (V_d) was −50 mV and the source was grounded (V_s = 0 mV). At 300 K, the subthreshold slope (S = dV_g/d log I_d) was 100 mV/decade, while the off current (I_off) was around −10 pA. As the temperature decreased to 3.8 K, S became steeper (14 mV/decade) and I_off was less than −10 fA, which was the expected behavior of CMOS transistors at low temperatures.^24,31 However, if the channel was considered to be uniform in the subthreshold region at 3.8 K, S should have decreased linearly as the temperature decreased, as $S=2.3kT1+Cdep,m/Cox/e$ indicates, where k is the Boltzmann constant, T is the temperature, e is the elementary charge, C_{dep, m} is the maximum depletion layer capacitance, and C_ox is the oxide capacitance.²⁴ This means that the hole channel is considered to be non-uniform, and the dominant current path is much narrower than the actual width of the device.

The presence of a QD can be directly verified from 2D contour plots of differential conductance (dI_d/dV_g) against V_g and V_d, shown in Fig. 2. I_d was measured twice as a function of |V_g| [from 0.5 V to 0.7 V with 1 mV increments (forward sweep), and from 0.7 V to 0.5 V with 1 mV decrements (reverse sweep)] with fixed V_d to check for the absence of hysteresis, and V_d was varied from −30 mV to 30 mV with 0.2 mV increments. Differential conductance was then calculated, and the result for the forward sweep is shown in Fig. 2. The compliance value of 1 μA was set to limit I_d, which corresponds to two zero conductance regions with |V_d| = 30 mV and |V_g| = −0.7 V. Hysteresis was not observed. Several CDs were observed, which are highlighted by dotted lines in Fig. 2. Two CDs with charging energy of about 5 meV (CD1 and CD2) were followed by a sequence of CDs with a smaller charging energy (CD3), 1 meV or 2 meV, as |V_g| increased. Two CDs with charging energy of 1 meV or 2 meV were also observed at |V_g| >0.65 V, which were labeled CD4 in Fig. 2. The presence of CDs, particularly CD1 and CD2, confirms that the dominant transport was through the QD after the transistor turned on. From the charging energy of the dot, the size of the QD can be estimated.^14,31 The charging energy (E_c) is first converted to the coupling capacitance of the QD, C_Σ by E_c = e²/C_Σ, which gives C_Σ = 32 aF. C_Σ can be decomposed into the coupling capacitance of the QD to source (C_S = 15.0 aF), drain (C_D = 5.42 aF), and gate (C_G = 11.62 aF) from the gradient of the CDs.^14,31 Finally, the size of the QD (S_QD) can be estimated from C_G = C_effS_QD, assuming that the C_eff is solely determined by t_eff, C_eff = ε_ox/t_eff = 1.44 μF/cm². ε_ox = 3.9ε₀ is the permittivity of SiO₂, where ε₀ is the permittivity of vacuum, 8.854 × 10¹²F/m. S_QD is 0.808 × 10⁻¹⁵ m⁻², and the diameter of the QD (⁠$dQD=4SQD/π$⁠) is about 32 nm when the shape of the QD is assumed to be round.³¹ The origin of the QD can possibly be remote surface roughness due to a poly-Si grain in the gate electrode.^31,32 The shrinkage of CDs (CD3 and CD4 are smaller than CD1 and CD2) can be attributed to the change in the inversion layer thickness.³¹ 

These two observations can confirm the transport mechanism in our device in the subthreshold region at low temperature. As |V_g| increased and the device began to operate at the subthreshold region, holes would start to flow through a QD first since it would provide the current path with low potential energy. After |V_g| exceeded the threshold voltage (V_th), on the other hand, a 2DHG was uniformly formed under the gate dielectric, and the same on current (I_on) of 0.2 mA at 300 K was achieved [Fig. 1(c)]. In the subthreshold region located between those two schemes, the carrier transport is thought to be described as a hybrid of the two mechanisms, where holes were predominantly traveling through a narrow, weak link between the source and drain involving the QD, resulting in the standard MOSFET characteristic being modulated by Coulomb blockades from the QD (Fig. 2), as well as the gentle subthreshold swing [Fig. 1(c)].

In order to investigate how dopants in the substrate affect the hole transport in the channel, positive substrate bias (V_well > 0) was applied such that the dopant ionization profile would be systematically changed. The application of positive substrate bias means that the p–n junction between the source/drain and the substrate was reversely biased, leading to more dopants becoming ionized and, therefore, fewer mobile holes being introduced from source/drain at a given |V_g| to satisfy charge neutrality,²⁴ 

where Q_tot is the total charge induced at a certain gate voltage, Q_dep is the ionized dopants in the substrate (depletion layer charges), Q_inv is the mobile holes introduced from the source/drain (inversion layer charges), and ΔQ_dep(>0) and ΔQ_inv(>0) are the increase and decrease in Q_dep and Q_inv, respectively, due to the reverse bias being applied to the substrate. This effect is called the “body effect,”²⁴ and |I_d| was expected to decrease as V_well increased, which is equivalent to a positive |V_th| shift.²⁴ 

In order to experimentally obtain Q_dep and Q_inv as a function of V_g and V_well, split capacitance–voltage (C–V) measurements with positive substrate bias⁴² were performed. From this split C–V measurements, one can quantitatively estimate how many dopants were additionally ionized by the positive V_well. This characterization was performed at room temperature using a Cascade probe station and the B1500. Two devices with (W, L) = (10 μm, 10 μm) (device B) and (10 μm, 4 μm) (device C) were measured, which were in the same wafer as the one measured at low temperature (device A), such that the extracted parameters from this measurement can be used for the interpretation of the measurement result obtained from device A. The use of two MOSFETs with different gate lengths is known to be helpful to eliminate parasitic capacitance and resistance.⁴³ Transfer characteristics with V_d = −50 mV were obtained prior to the C–V measurements, and the result from device B was subtracted from the one from device C to obtain I_d. Figure 3 shows drain conductance (g_d = I_d/V_d) against V_g, while V_well was varied from 0 mV to 500 mV with 50 mV increments. V_g was swept from 1 V to −1 V with 1 mV decrements, and the results were shown from 0 V to −1 V in linear scale to highlight the shift in |V_th|. |V_th| was 0.34 V when the substrate was unbiased (V_well = 0 V), and the shift in |V_th| toward positive |V_g| was clearly observed as V_well increased.

Then, in order to characterize capacitance of the devices, the AC signal with a frequency of 100 kHz and an amplitude of 100 mV was applied on top of V_g, which was swept from 2 V to −1 V with 1 mV decrements. The out-of-phase current was measured at (1) source and drain together [Fig. 4(a)], (2) substrate [Fig. 4(b)], (3) source, drain, and substrate, altogether, to characterize (1) inversion layer capacitance, C_inv = dQ_inv/dV_g (capacitance due to mobile holes), (2) depletion layer capacitance, C_dep = dQ_dep/dV_g (capacitance due to ionized donors), (3) total capacitance, C_tot = dQ_tot/dV_g (capacitance due to both ionized donors and mobile holes), while (1) V_well was applied from 0 V to 500 mV with 50 mV increments, (2) V_s = V_d was applied from 0 V to −500 mV with −50 mV decrements (equivalent to positive V_well), (3) N/A (source, drain, and substrate were all used to measure current and substrate bias cannot be applied) in order to see the effect of the positive substrate bias on the C–V profile. The capacitance measured from device B in those configurations was subtracted by the capacitance from device C and normalized by the difference in the transistor area between the two devices, 10 μm by 6 μm. To clarify, C_inv, C_dep, and C_tot are given as capacitance per unit area with the unit being μF/cm². From this split C–V measurements, Q_inv, Q_dep, and Q_tot are calculated as a function of V_g and V_well,

where V_gs = V_g − V_s is the gate voltage measured from the source.

Figure 4 shows C_inv, C_dep at various V_well values, and C_tot against V_gs. C_inv were plotted by solid lines with a color gradient from blue (V_well = 0 mV) to light green (V_well = 500 mV), while C_dep were plotted by solid lines with a color gradient from red (V_s = V_d = 0 mV, equivalent to V_well = 0 mV) to purple (V_s = V_d = −500 mV, equivalent to V_well = 500 mV). Orange empty circles show C_tot against V_gs, matching the result of C_dep with V_well = 0 mV in the accumulation region and C_inv with V_well = 0 mV in the inversion region.

C_inv shows its dependence on V_well in the inversion region (V_th > V_g), corresponding to the threshold voltage shift due to the body effect.²⁴ At a given V_g, C_inv is lower when positive V_well was applied, for example V_well = 500 mV,

Therefore,

This result is consistent with the physical picture described in Eq. (3).

As V_well increased, accumulation C–V curves are also shifted toward positive V_gs, meaning that flatband voltage (V_FB) is shifted by applying positive V_well. This is reasonable as the flatband condition is determined solely by the difference between V_gs and V_well − V_s, and, therefore, as V_well − V_s increased, more V_gs needs to be applied in order to achieve the same flatband condition. This parallel V_FB shift resulted in the increase in the maximum depletion layer charge Q_{dep, m} (Q_dep at |V_gs|≫|V_th|) by applying positive V_well, for Example 500 mV,

which is consistent with Eq. (2). Table I shows the calculated Q_{dep, m} at various V_well values, which proves the inequality (11).

So far, from the split C–V measurements, the overall trend expected from the body effect [Eqs. (2) and (3)] was experimentally proven. Furthermore, the depletion layer width can be quantitatively obtained as a function of V_g and V_well. This is equivalent to analyze the ionization profile of donors in the substrate as V_g and V_well changes, which gives further insight into the effect of applying V_well. To this end, the following model was employed:²⁴ 

which is valid when |V_gs| > |V_FB|. This model means that the total amount of Q_dep in the n-well per unit area can be described by the product of the substrate doping (donor) concentration (N_d) and the depletion layer width (W_dep). The spatial variation of N_d is ignored in this model and the precise value of N_d is not assumed a priori. First, N_d is determined from Q_{dep, m}(V_well = 0 V) and the maximum depletion layer width, W_{dep, m}. After |V_gs| exceeds the threshold voltage (|V_th|), the depletion layer width is expected to be constant, known as the maximum depletion layer width,²⁴ which is given as

where ε_Si = 11.9 ε₀ is permittivity of Si and n_i is the intrinsic carrier density of Si, 10¹¹ cm⁻³. This W_dep,m was assumed to be valid only when V_well = 0 V, and was used as a boundary condition to obtain N_d using Q_{dep, m}(V_well = 0 V),

which gives N_d = 5.97 × 10¹⁷ cm⁻³. This means that the average distance between the dopant atoms are 12 nm, which is in the same scale as the gate length of the device. Using this N_d, W_dep was calculated as a function of V_gs and V_well using Eq. (13), and plotted in Fig. 5. W_dep against V_gs were plotted by solid lines with a color gradient from red (V_well = 0 mV) to purple (V_well = 500 mV). As expected, W_dep becomes almost constant after |V_gs| exceeds the threshold voltage (−0.34 V) at any V_well. The inset in Fig. 5 shows W_dep at V_gs = −0.5 V as a function of V_well. This shows that in this model the rate of the depletion layer widening upon the application of V_well (dW_dep/dV_well) is almost constant about 20 nm/V.

By analyzing the change in the depletion layer width due to the application of V_well, it can be concluded that the reverse substrate bias can indeed systematically alter the donor ionization profile. The increase in ionized dopants in the substrate does not only reduce the minority carriers in the inversion layer, but also enhance the interaction between holes and ionized dopants by remote Coulomb scattering, resulting in the reduction of hole mobility. This can be experimentally confirmed by calculating effective hole mobility (⁠$μeff=LWgdQinv$⁠) against effective electric field [$Eeff=1εSi(Qdep+Qinv3)$] at various V_well values.⁴¹ Solid lines with a color gradient from blue to light green in Fig. 6 show the result, and the black dotted line is the universal mobility curve [$μuniv=185/(1+Eeff0.45)$] for the Si–SiO₂ interface. As can be seen from Fig. 6, the degradation of hole mobility is more prominent at low E_eff values, where the dominant scattering mechanism is remote Coulomb scattering between holes and ionized donors. At high E_eff, however, regardless of V_well values, all the mobility curves overlapped and approached the universal mobility curve. This means that the scattering at the Si–SiO₂ interface, the dominant scattering mechanism at high E_eff, has not increased much upon the application of V_well, and the enhanced interface scattering does not account much for the degradation of the hole mobility. The mobility degradation has been mentioned previously, and the mechanism was considered to be enhanced Si–SiO₂ interface scattering from qualitative discussion.^40,44 Our quantitative result reveals that the enhanced Coulomb scattering is the dominant mechanism to explain the mobility reduction by applying V_well.

The reliability of the C–V measurements was assured from good agreement with the numerical simulation based on analytical quantum mechanical model.⁴⁵ This model assumes the potential exponentially depends on the distance from the Si–SiO₂ interface, which allows one to find an exact solution of the Schrödinger equation. The solution is then fed back into Gauss’s law, which determines the parameter of the exponential potential, resulting in the self-consistent Poisson–Schrödinger equation.⁴⁵ The result of the C–V simulation is shown in Fig. 4 as a black dashed line, which agreed well with the experimental result with equivalent oxide thickness (EOT) of 2 nm being used as a fitting parameter. Other input parameters were N_d = 6 × 10¹⁷ cm⁻³ and V_FB = 1.01 V, which were determined from Eq. (15) and a maximum curvature of the C–V curve in the accumulation region, respectively. The difference between t_eff = 2.4 nm and EOT = 2 nm is attributed to the quantum confinement near the Si–SiO₂ interface, which can be converted into the width of the wavefunction in Si, t_Si = (t_eff − EOT) × ε_Si/ε_ox = 1.2 nm, which is reasonable.^31,45,46

After investigating the effect of the substrate bias on the dopant ionization profile in the substrate, detailed I–V scans with positive V_well were performed to see its effect on the hole transport in the device. Figures 7(a)–7(f) show 2D contour plots of I_d as a function of V_g and V_d at V_well = 0 V, 100 mV, 200 mV, 300 mV, 400 mV, and 500 mV. V_g and V_d were swept from −0.5 V to −0.7 V and 30 mV to −30 mV with 1 mV and 0.2 mV decrements, respectively, and the results within −0.7 V < V_g < −0.6 V and −15 mV < V_d < 15 mV are displayed. Even in the current range of sub-μA, the presence of CD4 can be clearly seen. In addition, as V_well increased, |V_th| shifted toward higher |V_g|, as expected. Another notable feature in Figs. 7(c)–7(e) is that a few discrete current peaks were observed, highlighted by arrows in the figures. Such current peaks were not observed when V_well = 0 V [Fig. 7(a)], and the number of current peaks seen in Figs. 7(a)–7(f) (V_well = 100 mV and 500 mV) is much less than in Figs. 7(c)–7(e) (V_well = 200 mV, 300 mV and 400 mV). This indicates that the peaks could only be observed around a certain V_well value. The current peaks were observed for both positive and negative V_d, and the ones in negative V_d (V_d < 0) are addressed in the following discussion. To clarify the nature of the current peaks, I_d–V_g curves with V_well = 200 mV and |V_d| varying from 7 mV to 13 mV with 1 mV increments are displayed in Fig. 8. Forward sweeps (increasing |V_g|) are shown with solid lines, while reverse sweeps (decreasing |V_g|) are shown with dotted lines. Discretized threshold voltage shifts of about 1.5 mV were observed around |V_g| = 0.65 V in Fig. 8, which coincides with the current peaks observed in 2D contour plots. The threshold voltage shifts continued to be observed with higher |V_d|. The inset of Fig. 8 shows the I_d–V_g curve with V_well = 200 mV and |V_d| = 30 mV, showing the same threshold voltage shift.

To confirm that the observed threshold voltage shift is caused by a single carrier,^47–49 |I_d| was monitored over 1000 s (time domain characteristics). The interval of measurements was 100 ms, and the integration time (included in the interval) was 20 ms. Figures 9(a)–9(e) show the time domain characteristic at various |V_g| (from large |V_g| to small |V_g|), while Figs. 9(f)–9(j) show corresponding histograms (probability to observe a certain current value) for each time trace. |V_d| was fixed at 30 mV to increase the signal to noise ratio between the high |V_th| state (=the low |I_d| state) and the low |V_th| state (=the high |I_d| state). When |V_g| was 0.62 V [Figs. 9(e)–9(j)], |I_d| was stable around 0.143 μA. The random switching between two states started to be observed at |V_g| = 0.639 V, which can also be identified from the two peaks in the histogram [Fig. 9(j)]. The probability of the two states was almost equal at |V_g| = 0.645 V, and the low current state was the dominant state at |V_g| = 0.655 V, indicating that the probability to observe one of the states is well controlled by the gate voltage. These |V_g| values coincide with the range of |V_g| in Fig. 8, where the threshold voltage shifts were observed, meaning that the nature of the shifts was RTSs. In addition, as the switching was between only two states, the hysteresis in |I_d| observed in Fig. 8 was due to trapping and de-trapping of a single carrier and no multiple charge states were involved.^47–49 At |V_g| = 0.725 V, |I_d| was stable around 5.02 μA and the random switching between two current states was not observed.

In Secs. II and III, the I–V and C–V characteristics of pMOSFETs at room temperature and low temperature were introduced, before unexpected observation of RTSs at 3.8 K by the application of positive substrate voltage (V_well) was shown in detail in Sec. IV. The biggest difference from conventional RTSs observed in CMOS devices^24–30 is that the RTSs were only observed when positive bias was applied to the substrate such that the depletion layer was further widened from its maximum width.^24,25 Although the modification of RTS parameters, such as Δ|I_d|, lifetime of the two current states (τ_High and τ_Low), by applying V_well was previously reported,^25,39 RTSs triggered by applying V_well have not been observed so far. As seen in Sec. III, the primary aim of applying the reverse substrate bias is to increase ionized donors in the substrate and widen the depletion layer, which results in a positive |V_th| shift. Therefore, we attribute the origin of the RTS to a dopant atom ionized by the application of positive V_well, capturing and re-emitting an electron and shifting |V_th| accordingly. The presence and absence of a single electron in the substrate and the resulting change in the depletion layer width could have a significant impact on the hole transport, as the effective width of the channel was limited by the size of the QD, about 32 nm, at low temperature (Fig. 1). Figure 10 illustrates the proposed physical model to explain the mechanism of the RTS. When V_well was grounded (0 V), a dopant atom was below the Fermi energy (E_F) and, therefore, filled with an electron, meaning that it could not affect the hole transport in the inversion layer [Fig. 10(a)]. As V_well increased, the depletion layer extended and the dopant level was subsequently raised, making the dopant level align with E_F [Figs. 10(b) and 10(c)]. Under this condition, both situations where the dopant was ionized or filled with an electron were energetically equally favorable such that switching between those two charge states would occur. A further increase in V_well would result in complete ionization of the dopant, and the dopant could not influence the transport anymore.

In order to justify this model, we estimate how much V_well is required to ionize one dopant under the QD, δV_well. The extension of the depletion layer, δW_dep, is defined such that the volume under QD (S_QDδW_dep) contains one donor, S_QDδW_depN_d = 1. This results in δW_dep = 2.1 nm, and, therefore, $δVwell=δWdep(dWdep/dVwell)−1$ is about 0.1 V, which is of the same orders of magnitude with V_well causing the RTSs. Considering the uncertainty associated with the size of the QD, this estimation is in good agreement with our observation.

This claim can also be supported from the direction of |V_th| shift due to RTSs. As |V_g| increased, the dominant current state shifted from the high |I_d| state to the low |I_d| state, corresponding to the positive threshold voltage shift (Fig. 9). This can be explained by the ionization of a single dopant due to the increased |V_g|. The dopant was initially well below E_F, before being brought into E_F by applying positive V_well. Then, as |V_g| increased, the conduction band bends further and the dopant level comes in resonance with E_F, resulting in an electron escaping and re-entering the donor level by quantum mechanical tunneling or thermal activation. This ionization contributed to the further widening of the depletion layer, leading to the positive |V_th| shift, consistent with the observation (Fig. 9). A further increase in |V_g| would result in complete ionization of the dopant, and RTSs would not be observed anymore.

In Sec. V, the physical origin of the RTS was suggested to be a dopant in the substrate, and two current states, high |I_d| state and low |I_d| state, were attributed to the two charge states, charge neutral and ionized, respectively. In order to study the mechanism of the RTS further, the statistics of the signal were investigated in detail.²⁵ Figure 11 shows the occupancy of each of the two current states, which is the probability to observe the high |I_d| state (N_High) or the low |I_d| state (N_Low) against gate voltage. N_High and N_Low were defined as follows:^33,34

where P(|I_d|) is the probability to observe a certain |I_d| value (Fig. 11), $⟨Id⟩=12(Id,High+Id,Low)$ is the average |I_d| value of the high |I_d| state (I_{d, High}) and the low |I_d| state (I_{d, Low}), and $IT=∫−∞∞P(|Id|)d|Id|$ is a normalizing factor. As |V_g| increased, N_High decreased and N_Low increased, which is consistent with the transfer characteristics (Fig. 8) as well as time domain measurement and their corresponding histograms (Fig. 9). At |V_g| = 0.645 V, N_High and N_Low became almost equal, meaning that under this bias condition, the high |I_d| state and the low |I_d| state were energetically almost equally favorable.

Asymmetry was found in N–|V_g| characteristics (Fig. 11) around |V_g| = 0.645 V. RTSs cannot be detected when |V_g| was smaller than 0.639 V, where the high |I_d| state dominates (about up to 80%). However, RTSs were still observed when |V_g| was more than 0.66 V, where the dominant low |I_d| state exceeded 80%. This asymmetry can be attributed to non-linear |I_d|–|V_g| characteristics.³⁴ First, |I_d| is not only susceptible to RTSs, but also disturbed by the analog noise such as shot noise,⁵⁰ thermal noise,^51,52 negative bias temperature instabilities (NBTIs),⁵³ noise from electrical component of these systems (cables, adapters, etc.), which would be overlaid onto the time traces of |I_d| and widen the probability distribution of |I_d| around the mean value. For RTSs to be detected, the amplitude of RTSs (Δ|I_d|) needs to be larger than the deviation around the mean value of each current state, which can be characterized by full width at half maximum (FWHM) of each current state. If |I_d| is a linear function of |V_g|, Δ|I_d| would be a constant value, and to the extent that the value is larger than FWHMs of both states RTSs should be detected, resulting in a symmetrical N–|V_g| characteristic. If |I_d| increases faster than a linear function (|V_g|² for example), Δ|I_d| would increase as a function of |V_g|,³⁴ and detecting RTSs would be difficult at small |V_g| since FWHM and Δ|I_d| are comparable. The inset of Fig. 11 shows FWHM of both the high |I_d| state (FWHM_High) and the low |I_d| state (FWHM_Low), and Δ|I_d| against gate voltage. A double Gaussian function was used to fit the probability against |I_d| to obtain FWHM_High, FWHM_Low, and Δ|I_d|. While Δ|I_d| and FWHM_High, FWHM_Low were comparable at |V_g| = 0.639 V, as |V_g| increased Δ|I_d| exceeded both FWHM_High, FWHM_Low, making it easy to distinguish two current states. Increasing the integration time may be useful to average out the fluctuation around the mean value of each current state.

The characteristic of RTS lifetimes (τ_High, time-to-emission and τ_Low, time-to-capture, defined in this paper), particularly its dependence on V_g, is considered to reflect the physical origin of the signal.^36,37,39 If the origin of the RTS is a trap in the oxide, the way the average lifetimes (⟨τ_High⟩ and ⟨τ_Low⟩) depend on V_g is considered to be asymmetric.^36,37,39 This is because the probability for a carrier to be captured by a trap depends on both the carrier density in the inversion layer and V_g. V_g determines the energy level of a trap with respect to Fermi energy, and as V_g increases, the trap level would become lower and it would be predominantly occupied. In addition, if the carrier density is higher, the chance of a carrier to be captured by a trap would increase further. The emission process, on the other hand, only depends on V_g as there is no other electron to be emitted. This difference in capture and emission process causes the difference in the behavior of time-to-capture and time-to-emission against V_g, where time-to-capture strongly depends on V_g, while time-to-emission is almost a constant.^36,37,39 Our model is based on a dopant exchanging an electron with n-doped well with fixed density of N_d, suggesting that both ⟨τ_High⟩ and ⟨τ_Low⟩ should be modified by |V_g|. Therefore, by calculating ⟨τ_High⟩ and ⟨τ_Low⟩ as a function of V_g, the observed RTS can be distinguished from the one caused by a trap in the oxide.

As far as the average values of τ_High and τ_Low (⟨τ_High⟩ and ⟨τ_Low⟩) are concerned, they can be efficiently obtained from the histogram of time differential of |I_d| (δI_d(t) = |I_d(t + Δt)| − |I_d(t)|), P(δI_d),³³ 

where T_High = N_HighT, T_Low = N_LowT, N_total is the total number of measurement points during T, and $δIT=∫−∞∞P(δId)dδId$ is a normalization factor. The denominator in Eq. (18) [(19)] is the number of transitions from the high (low) |I_d| state to the low (high) |I_d| state. Figure 12(a) displays ⟨τ_High⟩ and ⟨τ_Low⟩ against |V_g|. Similar to the N–|V_g| characteristics, two curves (⟨τ_High⟩–|V_g| and ⟨τ_Low⟩–|V_g|) were crossing at |V_g| = 0.645 V. While the dependence on |V_g| is different, both ⟨τ_High⟩ and ⟨τ_Low⟩ were modified by |V_g|, meaning that the result suggests that the physical origin of the RTS could be a dopant and also different from a trap in the oxide. Further advanced measurements, such as single-electron spin resonance⁸ can be a next logical step, which is, however, out of the scope of this paper.

Figures 12(b) and 12(c) are the probability distribution of individual transitions (from the high |I_d| state to the low |I_d| state and from the low |I_d| state to the high |I_d| state, respectively) when |V_g| was fixed to 0.645 V. For this particular measurement, I_d was monitored for 10 000 s with Δt being 1 s so that the longer time trace could be taken without increasing the data points, while Δt was short enough to capture the RTS with average lifetimes of 20 s. The distributions can be well approximated by an exponential curve, indicating that there was no periodicity in this signal and also the finite detection bandwidth of the measurement did not affect the statistics of the observed RTS.⁵⁴ 

From the analysis on ⟨τ_High⟩ and ⟨τ_Low⟩ as a function of V_g, a dopant in the substrate is considered to be a realistic candidate of the physical origin of the observed RTS. In order to further validate this physical model, finally, the device was measured at temperatures up to 25 K. RTSs were observed at a similar |V_g| range at higher temperatures as well. The rise in the temperature certainly shifted the threshold voltage, though the statistics of RTS has not been significantly changed, as can be seen from Fig. 11. N–|V_g| characteristics at 12 K are shown in Fig. 11, and similar to the case of 3.8 K, N_High–|V_g| and N_Low–|V_g| curves cross at |V_g| = 0.645 V, meaning that both states were observed equally frequently at 12 K as well. Then, time domain measurements were taken at |V_g| = 0.645 V and different temperatures (5 K, 7 K, 10 K, 11 K, 12.5 K, 14 K, 16 K, 20 K, and 25 K). Figure 13 shows the average lifetimes of the high and low |I_d| state against the inverse of temperature T (1000/T), while |V_g| was fixed to 0.645 V. This graph indicates that the lifetimes were temperature independent up to 16 K and became faster as the temperature rose to 20 K and 25 K.

This trend can be understood in a way that the mechanism of the trapping and detrapping of an electron transit from quantum mechanical tunneling at low temperature to thermal activation at higher temperatures,³⁸ 

where P_quantum and P_thermal are probability for an electron to become trapped or detrapped via quantum mechanical tunneling and thermal activation per 1 s, τ_q is an attempt interval for the quantum mechanical tunneling to occur, ΔE is the activation energy for the thermal activation process to occur, τ_th is an attempt interval for the thermal activation provided the activation energy is negligibly small, and τ_experiment is the experimental data, such as τ_High and τ_Low. This model means that the total probability of trapping and detrapping of an electron can be described by the sum of the probability of such a carrier exchange to occur via quantum mechanical tunneling and thermal activation. The inset of Fig. 13 describes two mechanisms in an energy band diagram. The orange arrow represents thermal activation, where an electron escapes from a dopant with thermal activation, similar to how free carriers are provided in the conduction band of bulk Si. The green arrow describes the quantum mechanical tunneling, where an electron tunnel through the potential barrier between a dopant and a highly doped region. We used this model to qualitatively explain the temperature dependence of the average lifetimes. The orange dotted line in Fig. 13 is an Arrhenius plot with ΔE of 26 meV, requirement for a dopant to provide carriers at room temperature, and the green dotted-dashed line shows the average value of the lifetimes at the temperatures from 3.8 K to 14 K, 18.04 s. These two lines can approximately reproduce the trend observed in Fig. 13. This result indicates that the coupling of a single dopant to the electron reservoir (well) at 3.8 K is quantum mechanical, indicating that the system in our device can be described by the renowned single impurity Anderson model.⁵⁵ Quantum tunneling rates can also be associated with the analytic solutions in the case of biased double-well systems.^56,57

In this paper, the observation of random telegraph signals caused by a single dopant in the substrate of a p-type metal–oxide–semiconductor field-effect-transistor was reported. RTSs were initially not observed until the substrate bias was applied such that the depletion layer becomes widened. Trapping and detrapping of an electron changed the depletion layer width under the narrow channel involving a quantum dot, which worked as a sensitive charge sensor. Statistics of the individual lifetime of the RTSs obeyed the exponential distribution, and the occupancy of the two current states and lifetime were controlled by the gate voltage, as expected. Average lifetimes associated with the discrete current states were significantly modified by gate voltage, indicating that the origin of the signal differs from trap states in the oxide. The temperature dependence of the average lifetime indicates that the tunneling mechanism transited from quantum mechanical tunneling to thermal activation as the temperature increased. Engineering of atomic-scale features and manipulation of a single carrier are crucially important for quantum technology for nanoelectronics,^{1–4,14–16} for metrology,^{5,10,11,20,21} and even for quantum information processing.^{6–9,17–19} We focused on a dopant in the substrate and realized single-electron manipulations in an industry-grade Si MOSFET in a reasonably easy manner at a relatively higher temperature of 3.8 K. Our work proposes an alternative approach to utilize the existing yet to date little considered candidate of such an atomic-scale feature, a solitary dopant in the substrate, for future quantum application.

K.I., Z.L., M.K.H., and S.S. prepared samples for measurement. K.I., J.H., F.L., Y.T., H.R., and S.S. established measurement setup for room temperatures and cryogenic temperatures. K.I., J.H., and S.S. designed the experiments, and K.I. performed measurements. S.S., K.I., and I.T. proposed the physical model of the observed random telegraph signals. K.I. analyzed data and drafted the manuscript. All authors participated in discussion.

The data that support the findings of this study are openly available in ePrints Soton, the University of Southampton Institutional Research Repository (https://doi.org/10.5258/SOTON/D1193).⁵⁸ 

This work was supported by the EPSRC Manufacturing Fellowship (Grant No. EP/M008975/1), the Lloyds Register Foundation International Consortium of Nanotechnology, and the Joint Research Project [No. e-SI-Amp (15SIB08)]. This work was also supported by the European Metrology Programme for Innovation and Research (EMPIR) co-financed by the Participating States and by the European Union’s Horizon 2020 research and innovation program.

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.