Great efforts have been made in the past few years to reduce the white pixel noise in complementary metal–oxide–semiconductor (CMOS) image sensors. As a promising approach, the surface passivation method focusing on the field-effect passivation has been studied in this work. Based on the metal–oxide–semiconductor capacitor device model, electrical measurement and analysis have been performed for characterizing the charge distribution in the system. The relationship between the flat band voltage and the white pixel performance has been set up, and the proposed passivation method that controls Si or SiO2 interface charge or traps has been proved effective in lowering the white pixel noise, which can be very attractive in improving the performance of CMOS image sensors for high-resolution and high-sensitivity applications.
In the past two decades, the complementary metal–oxide–semiconductor (CMOS) image sensors (CISs) have been widely used in cell phone cameras, security cameras, automotive electronics, and so forth due to the low cost and good control over blooming.1,2 A traditional front-illuminated CIS is manufactured in an architecture similar to the human eye, with a set of lenses in the front and the photodetector at the back side. However, this structure can lead to an unexpected reduction in signal intensity because of the reflection of light at the front-side, leading to reduced capability of high-quality imaging. Therefore, a backside illuminated (BSI) CIS device has intrinsic advantages over the front-illuminated counterparts for its higher sensitivity and better crosstalk, which will make it a promising candidate in the vast infrastructure current technology.3–5
White pixel (WP), considered as a noise reflecting on a dark image without correction (virgin image), is a key index indicating the quality of an image sensor. In general, WP is defined as the outlier pixel counted on one block pixel dark image. When the pixel with a gray level is higher than the average value of all pixel arrays, it is counted as a WP.6,7 In order to improve the device quality, all the major CIS manufacturers focus on the reduction of WP via design, process, contamination control, and so on. From the pixel design, the pinned photodiode is introduced to suppress the surface state and stabilized photodiode electrically,8 and a shallow boron-doped layer on the backside using ion-implant-laser anneal (IILA) is also investigated to suppress the un-passivated dangling bonds at or near the back surface.9,10 From the standpoint of the process, the vertical transfer gate (VTG), front-side deep trench isolation (DTI), and buried shielding metal (BSM) have been demonstrated with equal or advanced characteristics to extend the pixel pitch scaling limit.11,12 To reduce contamination, ultra-clean technology including various gettering methods to catch excessive vacancies and metals have been proposed to keep metallic contaminants away from the depleted photodiode area.13–15 Moreover, some other novel methodologies have also been studied. For example, a macroscopically flat device using the p + region for pixel isolation instead of STI to avoid damage and stress in the process in the pixel area has been developed to achieve high saturation signal capacity with low dark current (DC).16
Specifically, BSI WP reduction can be regarded as a DC improvement, attributed to a minimized charge carrier recombination loss at the crystalline silicon surface or interface.17 Thus, two strategies can be considered: (i) chemical passivation to reduce the defect states such as uncoordinated atom bonds;18 (ii) field-effect passivation by means of free charge carrier reduction. In this work, several key processes in the BSI technology correlated with WP have been investigated. The interface traps and flat band effect by measuring the metal–oxide–semiconductor capacitor (MOS-CAP) structures were also studied.19,20 Furthermore, compared to the industry practice, these passivation approaches have proved that controlling Si or SiO2 interface charge or traps is an effective method to improve the WP performance in CIS devices.
The BSI structure [Fig. 1(a)] could be simplified as the MOS-CAP model [Fig. 1(b)]. As shown in Fig. 1(b), the MOS-CAP configuration consists of three regions: the top metal layer (aluminum with a thickness of 1450 nm), bulk oxide layer [stacked film of 130 nm SiO2/60 nm high-k constant (HiK) dielectric/1 nm SiO2], and silicon substrate. The MOS capacitor is utilized as a test device to measure high-frequency (100 kHz and 27 °C) capacitance–voltage (C–V) characteristics, a perfect structure for routine fabrication process control as well as a tool for more detailed diagnostics.21 In addition, together with the conductivity–frequency (G–F) plot, the electrical tests were performed to derive the indicators of flat band voltage (Vfb), peak conductivity (Gpeak), and charge distribution in a pixel structure through scanning capacitance microscopy (SCM).
For chemical passivation, different high-k films, such as HfO or AlxOy, have been investigated in some reported work and our previous study to achieve a better control on substrate charge.22 From SCM analysis of charge distribution in the pixel structure (Fig. 2), with SiO2 deposition, the p-substrate inverses a large amount of negative charge under the photodiode [Fig. 2(a)], which provides a leakage tunnel. After HiK film formation, most of the negative charge is decreased [Fig. 2(b)], thus, the pixel isolation is strengthened through this passivation method. However, it should be noted that there is still some charge remaining on the silicon interface, which is a potential source of WP or DC.
In this work, to improve the remaining charge on the silicon interface, the field-effect passivation approach was studied and two process flows involving different alloy methods after Si oxide deposition were performed: the final alloy method (FA) and the SiN alloy (NA) method (Fig. 3). The impacts of the two process flows on the WP performance were compared. In the FA alloy process [Fig. 3(a)], the process flow was carried out as high-k layer and silicon dioxide deposition, metal pad formation, and alloy annealing; while in the NA alloy method [Fig. 3(b)], the flow sequence was arranged as high-k layer, silicon dioxide, and silicon nitride deposition, alloy annealing, nitride etch back,23 and, then, metal pad formation. The gas atmosphere during annealing was a mixture of N2 and H2, which is effective for decreasing the interface charge density Dit.18 The WP and DC performance were verified on a 3264 × 2448 sensor array with 1.1 µm pixel pitch.
RESULTS AND DISCUSSION
For the field-effect passivation study, a higher Vfb could be obtained for the NA sample from the C–V plot, with the Vfb shifted from 17.3 V (FA) to over 25 V (NA) (Fig. 4). Figure 5 illustrates the G–F (conductivity–frequency) plots for the two samples. Contrary to the positive Gpeak obtained from the FA sample, an additional negative Gpeak at 2.7 GHz was obtained from the NA sample.
One possible reason is that the interface traps were reduced during the nitride alloy annealing. The SiN film contains a high concentration of hydrogen, which can be released during annealing. Some of the hydrogen atoms diffuse into the Si/SiO2 interface and react with the interface traps (Si dangling bonds24,25) during the annealing process, making them electrically inactive (schematically illustrated in Fig. 6). Meanwhile, a silicon nitride layer can block the migration of hydrogen from the film, and, therefore, Gpeak moves to the positive direction. The model of this interface passivation approach can be referred to the practical situation in which hydrogen is generated from the Back-End-Of-Lines (BEOL) layers with nitride layer capping and then diffuse down into the silicon surface to fill the dangling bonds.26
The measurement results of WP performance for field-effect passivation were compared in Fig. 7. It can be easily distinguished that the performance of the NA condition sample is lower and have a thicker distribution than the FA condition one. From the box chart shown in Fig. 8, an obvious DC improvement is observed in the NA condition sample. These experimental results confirm that controlling the silicon interface charge through the NA method is beneficial for better WP and DC performance.
A study of white pixel reduction was performed by improving the passivation approaches. For the field-effect passivation approach, by changing the alloy annealing process, an evident improvement in the WP performance was observed in the modified nitride alloy annealing samples as compared to the reference sample. This is due to the diffusion of hydrogen atoms into the Si/SiO2 interface and the reaction with the interface traps (Si dangling bonds), making them electrically inactive and resulting in a higher Vfb. This study provides an effective method for WP reduction in the fabrication of high-quality CMOS image sensor pixels.
The data that support the findings of this study are available from the corresponding author upon reasonable request.
This work was supported by the NSFC (Grant Nos. 61704030 and 61522404), the Shanghai Rising-Star Program (Grant No. 19QA1400600), and the Program of Shanghai Subject Chief Scientist (Grant No. 18XD1402800).