Fan-out enabled spin wave majority gate

The rapid increase in available row data led to an abrupt downscaling of the CMOS technology in order to meet the continuously increasing application demand for high performance computation platforms.¹ However, CMOS scaling became more and more difficult due to various technological hurdles, such as (i) quantum mechanics related phenomena and physical limitations, such as leakage;² (ii) high failure rate and short lifetime of devices;³ and (iii) steep fabrication cost increase not justifiable by scaling economical benefits.² As a result, different emerging technologies are now explored as potential candidates for future partial/total CMOS replacement.^4,5 One of them relies on Spin Wave (SW) interference within magnetic waveguides.^4,5 Preliminary investigations suggest that SW based computing potentially enables ultra low power consumption at acceptable delay and has great scalability potential.^4,5 SW computing is based on wave interference, which can be either constructive or destructive depending on the interfering SW phases. This principle is used to build SW logic gates. A spin wave interferometer, e.g., Mach–Zhender interferometer, was used to investigate this phenomenon.^6–10 To this end, different logic and Majority gate designs were introduced;^11–21 they all, with the exception of Refs. 16 and 17, make use of bent waveguides through which weak signals as SWs do not properly propagate and attenuate very fast.

As the 3-input Majority gate (MAJ3) together with an inverter forms a universal Boolean logic gate set, it provides the foundation for the potential implementation of complex SW circuits.¹¹ However, building larger circuits requires gates with fan-out capability, which none of the previously mentioned designs possesses. Thus, if a certain Majority gate has to provide its output to more than one gate input, it has to be replicated. For example, if a gate output has a fan-out f > 1, all the gates on its cone of influence starting for the circuit primary inputs have to be replicated f times. Given that practical circuits include many such gates, the lack of fan-out capability results in substantial area and energy consumption overheads. The SW circuit fan-out issue has been addressed, and magnonic splitter^22–25 or caustic beam²² based solutions have been proposed. However, the presented designs require large frequency bands and are not scalable. If the magnetic field is applied in plane, the T-shape magnonic splitter²³ relies on the SW mode (backward volume and surface) conversion. Given that the dispersion relation is magnetic field direction dependent, such an approach results in complex SW interference patterns, which precludes the utilization of T-shape magnonic splitters in the design of large SW circuits. The possibility to implement a magnonic splitter by voltage controlled reconfigurable nano-channels was discussed in Ref. 24; however, no detailed analysis of the spin wave quality after splitting has been provided. Additionally, a nonlinear directional coupler that allows SW transmission from a waveguide to another was investigated²⁵ and demonstrated the SW power dependency of this phenomenon. However, this concept splits the SW energy and cannot provide SW replication, which is crucial for gate fan-out achievement.

In view of the above, it can be concluded that SW based computing with potential ultra low energy consumption cannot become reality without gate intrinsic fan-out capabilities. Here, we overcome this challenge and introduce a generic SW Majority gate structure that provides natural fan-out support. Our structure is based on an area efficient 3-input Majority ladder-shaped SW gate structure that is able to provide a maximum fan-out of 2. This concept has been validated by means of micromagnetic simulations with the Object Oriented Micromagnetic Framework (OOMMF).

Generally speaking, the proposed gate can operate with any SW type; however, each SW type has its proper dispersion relation, which plays a crucial role in the actual gate design. Magnetostatic Spin Waves (MSWs) can be classified into three limiting cases: Magnetostatic Surface Spin Wave (MSSW), Backward Volume Magnetostatic Spin Wave (BVMSW), and Forward Volume Magnetostatic Spin Wave (FVMSW).²⁶ Depending on the wave propagation direction, BVMSW and MSSW exhibit different dispersion relations. This complicates the circuit design because similar SW propagation in both horizontal and vertical directions is required. For FVMSWs, which propagate in a plane perpendicular to the static magnetization orientation, SW exhibits the same dispersion relation regardless of the wave vector orientation. In this view, we rely on them in the gate design introduced in the following lines.

Different SW excitation (and detection) methods exist, e.g., microstrip antennas,^27,28 magnetoelectric cells,^29–31 spin–orbit torque.^32,33 A spin wave propagates through the waveguide with a wavelength λ, frequency f, amplitude A, and phase ϕ. Information can be encoded in its amplitude, phase, or both of them. If multiple SWs coexist in a waveguide, the computation can be performed using wave interference. Two waves with the same λ, A, and f can interfere constructively or destructively depending on their relative phase difference: (i) in-phase SWs interfere constructively and the resulting wave has a doubled amplitude and (ii) out-of-phase SWs interfere destructively, and therefore cancel each other. If more than two equal λ and f SWs interfere, the result reflects a Majority decision, i.e., if more SWs have ϕ = π (logic “1”) than ϕ = 0 (logic “0”), the resultant SW has ϕ = π, and ϕ = 0 otherwise. This means that the SW interference provides natural support for direct (no Boolean gates are required) Majority gate implementations. For example, a CMOS implementation of a 3-input Majority gate requires 18 transistors, whereas a single magnetic waveguide is enough for the SW counterpart.^11,16 In the linear regime, it is possible to have simultaneous propagation of spin waves with different frequencies. The information can be encoded in the phase of the spin wave at each and every frequency, and therefore, SW gates inherently enable parallel computation on shared hardware resources. Additionally, if the involved waves have different amplitudes, they still interfere constructively or destructively depending on the phase difference. However, this generates multiple SWs with different amplitude values, which could be beneficial for the realization of multi-valued logic gates. In the most general case, SWs with different amplitudes, phases, wavelengths, and frequencies can be excited and intricately interfere in the same waveguide. This provides promising alternative avenues toward novel, yet to be discovered, SW based computing paradigms and systems.

In this paper, we propose a 3-input Majority gate (MAJ3) that has a ladder-shape structure, as depicted in Fig. 1. The inputs are excited at (I₁, I₂, I₃, and I₄) and the outputs are read from (O₁, O₂).

To obtain a proper interference pattern at the crosspoints, the waveguide width w has to be less than or equal to the wavelength λ. Also, the excited SWs should have the same amplitude A. In addition, all excited SWs are required to have the same frequency to achieve the desired interference pattern. We propose a generic device layout, its dimensions, and some critical distances d_i (where i = 1, 2, …, 7) expressed in terms of spin wave wavelengths, as indicated in Fig. 1. For example, if λ wavelength SWs have to constructively interfere when they have the same phase and destructively otherwise, d₁, d₂, d₃, d₄, and d₅ must be equal with nλ(n = 1, 2, 3, …). If the opposite behavior is targeted, d₁, d₂, d₃, d₄, and d₅ must be equal with $n2λ(n=1,3,5,…)$⁠. Moreover, to obtain a proper fan-out of 2, i.e., outputs with the same energy levels, the structure has to be symmetric, and thus d₁ to d₅ must have the same value.

In contrast with CMOS gates, SW gates can provide both direct and inverted output by properly adjusting the output transducer position vs the output interference point. In this way, the direct and inverted result can be read at a distance of nλ(n =1,2,3,…) and $n2λ(n=1,2,3,…)$ from the last interference, respectively. In our case, MAJ (a, b, c) and $MAJ¯(a,b,c)$ are obtained at d₆ = d₇ = nλ(n = 1, 2, 3, …) and d₆ = d₇ = $n2λ(n=1,3,5,…)$⁠, respectively, and both outputs exhibit the same energy because of the structure symmetry.

Intuitively speaking, the Majority gate operates as follows: (i) SWs with appropriate phases are initiated at I₁, I₂, I₃, and I₄ to the targeted logic value (0 or 1). (ii) The excited SWs propagate (in both directions in the horizontal and vertical waveguides) and interfere when meeting each other. The resulting wave propagates toward the outputs O₁ and O₂. Thanks to the symmetry of the device and the isotropic behavior of the spin waves in this configuration, the waves arriving at the gate outputs are identical, and thus, the 3-input Majority gate exhibits a fan-out of 2. It is worth mentioning that I₃ has an effect on O₂ as the spin wave signal excited at I₃ propagates through I₁ and I₂. Also, I₄ has an effect on O₁ as the spin wave signal excited at I₄ propagates through I₁ and I₂. In addition, spin wave excited at I₁ and I₂ face edges, while its propagation to the output, in contrast to I₃ and I₄, which have a straight path to the outputs. Therefore, I₃ and I₄ are excited at lower energy than I₁ and I₂ as will be discussed further later in this paper.

It is worth mentioning that I₃ has an effect on O₂ as the SW excited at I₃ propagates through I₁ and I₁. Similarly, I₄ has an effect on O₁ as the spin wave signal excited at I₄ propagates through I₁ and I₂. In addition, SWs excited at I₁ and I₂ face edges, while they propagate toward the outputs, while I₃ and I₄ generated SWs have a straight path to O₁ and O₂, respectively. Therefore, I₃ and I₄ are excited at lower energy than I₁ and I₂ as will be discussed further in this paper.

We validate the proposed majority gate by means of micromagnetic simulations while making use of Fe₆₀Co₂₀B₂₀ waveguides, with a Perpendicular Magnetic Anisotropy (PMA) field greater than the magnetic saturation, which means that no external magnetic field is required for proper gate operation. We instantiated a MAJ3 gate for waveguide width w = 75 nm, and to simplify the interference pattern, we selected a larger wavelength than w, SW wavelength λ = 165 nm, which implies that d₁ = d₂ = d₃ = d₄ = d₅ = d₆ = d₇ = 165 nm. Furthermore, we assume the following values of the relevant parameters:³⁴ magnetic saturation M_s = 1.1 × 10⁶ A/m, exchange stiffness A_exch = 18.5 pJ/m, damping constant α = 0.004, perpendicular anisotropy constant k_ani = 8.3177 × 10⁵ J/m³, and waveguide thickness t = 1 nm. We calculated the FVMSW dispersion relation for these parameters, and for λ = 165 nm, and k = 2π/λ = 38 rad/μm, the SW frequency is determined to be f = 6.5 GHz. To get some indication of the MAJ3 scaling implications, we also designed smaller structures, e.g., w = 50 nm, with λ = 110 nm and f = 9 GHz. This makes the distances d₁ = d₂ = d₃ = d₄ = d₅ = d₆ = d₇ = 110 nm.

The proposed design combines two Majority gates operating in parallel on the same input set as can be observed in Table I. I₁, I₂, and I₃ constitute the first Majority gate with its output being detected at O₁, whereas I₁, I₂, and I₄ constitute the second Majority gate with O₂ as the output. Figure 2 presents OOMMF simulation results for the proposed w = 75 nm and w = 50 nm MAJ3 gates, under all possible input combinations. Note that in the figure, blue presents logic “1” (i.e., phase of π), red presents logic “0” (i.e., phase 0), the input order is (I₃ I₂ I₁) and (I₄ I₂ I₁), and (i), (ii), (iii), (iv), (v), (vi), (vii), and (viii) capture the gate reaction to (0 0 0), (0 0 1), (0 1 0), (0 1 1), (1 0 0), (1 0 1), (1 1 0), and (1 1 1) input patterns, respectively. As can be observed from Fig. 2, the results are in agreement with the MAJ3 truth table in Table I. If I₁ = I₂ = I₃ = 0 or the majority of the inputs are 0, then O₁ = O₂ = 0 (red), whereas if the majority of the inputs are 1, then the outputs O₁ and O₂ are 1 (blue), as expected. In addition, it can be noticed in Fig. 2 that the scaling does not affect the functionality of the Majority gate.

Figure 3 presents the possibility of having the inverted and non-inverted outputs by adjusting the reading position. As one can observe in Fig. 3, the inverted output (O′₁ and O′₂) of the Majority gates can be obtained by just shifting the reading position to a $n2λ$ position.

By post-processing the OOMMF simulations, we estimated the MAJ3 gate delay, i.e., the maximum time it takes for the inputs to propagate to the output, as 1.5 ns and 1 ns for the w = 75 nm and w = 50 nm structures, respectively. To investigate the waveguide width reduction influence on the SW group velocity Vg, we calculated the group velocities from micromagnetic simulation and obtained Vg_50nm = 1.15 μm/ns and Vg_75nm = 1 μm/ns for w = 50 nm and w = 75 nm structures, respectively. We also note that SWs are traveling shorter distances for the smaller structure, e.g., distance I₃ to O₁ is 380 nm for w = 50 nm and 570 nm for w = 75 nm. This implies that the I₃ to O₁ propagation takes 330 ps for w = 50 nm and 570 ps w = 75 nm. Therefore, the gate performance increase is a consequence of both shorter traveling distance and increased group velocity. Thus, the gate delay can be further reduced by scaling down w, but also by making use of other waveguide materials.

We note that if only one MAJ3 output is required, then the structure can be simplified: (i) physically, by removing one of its vertical waveguides (arms) or (ii) logically, by not providing an input signal to I₄. Moreover, the gate fan-out capabilities can be extended beyond two by vertically lengthening its arms. For example, if the outputs in Figs. 2 and 3 are shifted downward to the end of the arms and two outputs are placed upward (at the upper-end of the arms), four outputs can be accommodated and if properly designed, the gate can provide a fan-out of 4 as indicated in Fig. 4. However, the detailed design of such a structure constitutes future work and is out of the scope of the current paper.

To get inside on the quality of the achieved fan-out, i.e., the similarity between the two SWs obtained at the gate outputs, we make use of Magnetization Spinning Angle (MSA) as metric. The input and output spinning angles are calculated as

where $mx¯$ and $my¯$ are the x and y components of the magnetization, respectively.

Table II presents the contribution percentage of each input to the outputs O₁ and O₂ when each of them is separately activated, for the 50 nm waveguide width design. The output MSAs in the table are normalized values with respect to the activated input MSA. Thus, when only I₁ is activated, O₁ and O₂ MSAs are normalized by I₁ MSA. The same holds true for the other three situations presented in the table. As it can be noticed, I₃, I₂, I₁, and I₄ contributions to O₁ and O₂ are quite different. Due to the symmetry, I₁ equally contributes to both gate outputs O₁ and O₂ and the same holds true for I₂ also. However, due to its proximity, I₂ has a larger contribution to the outputs than I₁ and as such their strengths have to be properly balanced. Input I₃ SW is the strongest contributor to O₁ as it has a direct path to O₁, while spin waves from I₂ and I₁ are facing edges and reflect back and forth. Moreover, I₃ mostly affects O₁ and to a lower extent O₂, while the I₄ effect is stronger on O₂ and weaker on O₁. Thus, as the inputs on the vertical and horizontal waveguides differently contribute to the outputs, I₃ and I₄ SWs must be excited at lower energy than I₁ and I₂ SWs to enable the correct gate behavior.

Table III presents the normalized (with respect to I₁) MSA of the outputs when all inputs are activated together for the same w = 50 nm design. As it can be noticed from Table III, the normalized O₁ and O₂ MSA is the same in all cases, which means that the proposed MAJ3 gate can successfully achieve a fan-out of 2. One can also observe in the table that different input combinations are producing different normalized MSA values. When all gate inputs have the same value (I₁ = I₂ = I₃), the output MSA is reaching the highest value because of the constructive interference. When inputs have different values, the destructive interference diminishes the spin wave energy, which results in lower MSA values. Moreover, when the horizontal inputs (I₁ and I₂) are different, the position of the asserted input affects the MSA output. For example, when (I₃ = 1, I₂ = 0, and I₁ = 1) or (I₃ = 0, I₂ = 1, and I₁ = 0), the normalized output MSA is higher than when (I₃ = 1, I₂ = 1, and I₁ = 0) or (I₃ = 0, I₂ = 0, and I₁ = 1) because I₂ is located further than I₁ and I₃ from the interference location. As a result, when I₁ and I₃ have the same state, they interfere constructively and then destructively with I₂, which results in a larger magnetization angle.

An accurate evaluation of the proposed structure is not possible at this stage of development, especially for the energy and delay. That is mostly due to the missing excitation and detection cell figure of merit data. Thus, as the transducers are the dominant source for energy and delay, we chose to use the area as a metric to position our proposal vs the existing state of the art.

In order to make a fair comparison with Ref. 12, we scaled down the MAJ3 design for w = λ = 48 nm and validate it by means of OOMMF simulations. In addition, the outputs are captured directly at the last interference point. The proposed scaled FO2 MAJ3 gate requires a real estate of 0.0576 µm². As the gate in Ref. 12 cannot provide fan-out, we have to consider two such gates working in parallel on the same input set to evaluate both gates in similar utilization conditions, which results in a required area of 0.0691 µm², i.e., our proposal provides a 16% area reduction at the gate level. We note, however, that at the circuit level the area savings are significantly more substantial, as, in order to deal with a fan-out of 2 gate output O, the approach in Ref. 12 requires the replications of all the gates on O’s cone of influence starting from the circuit primary inputs, and that for efficient logic synthesis of practical circuits, gates with >1 fan-out are frequently necessary.

In order to compare with CMOS, we evaluated a 3-input Majority gate implemented in 15 nm technology with two NAND gates and one OR-AND-Invert (OAI) gate, at V_dd = 0.8 V, 25 °C, and an output load capacitance of 20 fF. Our evaluation indicates that the 15 nm CMOS MAJ3 area is 0.688 µm², thus a 12× larger area than the proposed SW MAJ3 gate.

In summary, we presented a novel fan-out of 2 area efficient 3-input spin wave Majority gate (MAJ3). We validated two instances of our proposal by means of OOMMF simulations and evaluated the fan-out quality by making use of the Magnetization Spinning Angle (MSA) as the metric. We calculated the normalized MSA values for the gate outputs and obtained negligible mismatch between them under all possible input combinations, i.e., a high quality fan-out. We compared our proposal with MAJ3 SW, under the same material assumptions and utilization conditions, and 15 nm CMOS state-of-the-art counterparts in terms of area and demonstrated a 16% and 12× less area, respectively. As a closing remark, we note that achieving >1 fan-out is an enabling factor for the realization of SW circuits as it eliminates the otherwise required circuit replication associated with fan-out nodes intrinsic to SW circuits produced by means of logic synthesis. Thus, the implications of our proposal at the circuit level are a lot more substantial than at the gate level, both in terms of area and energy consumption.