Design of an erasable spintronics memory based on current-path-dependent field-free spin orbit torque

The traditional memories such as static random access memory (SRAM) and dynamic random access memory (DRAM) are facing the bottleneck of the soaring static power consumption, due to the increasing leakage currents with the scaling of the CMOS transistors. Emerging non-volatile memories promise to replace SRAM and DRAM for overcoming the above bottleneck. Among them, spin transfer torque magnetic RAM (STT-MRAM) is one of the most promising candidates for constructing the next-generation low-power and high-density non-volatile memory.¹ However, the write speed of the STT-MRAM is limited to tens of nanoseconds, which cannot meet the requirement of SRAM-based caches. In this situation, spin orbit torque (SOT)-MRAM has recently attracted massive research interests since it could achieve sub-nanosecond switching and shows great application potential in the upper level caches.^2–5 

The conventional SOT device is composed of a magnetic tunnel junction (MTJ) deposited above a heavy metal layer. A current passing through the heavy metal layer can switch the MTJ between high and low resistance states, due to the spin Hall effect⁶ or Rashba effect.⁷ Thus data ‘1’ and ‘0’ can be written according to the directions of the current. For achieving high density and ultrafast switching speed, the magnetic anisotropy of the MTJ is preferred to be perpendicular. However, for the perpendicular-anisotropy SOT-MRAM, an undesirable magnetic field is required to break the symmetry and make the switching become deterministic, which is a burden for the practical MRAM products. Thus field-free SOT mechanisms have been widely proposed.^8–16 

Recently, we proposed a novel field-free SOT mechanism for the deterministic switching of the perpendicular-anisotropy MTJ.¹⁷ The device structure is shown in Fig. 1, where an elliptical perpendicular-anisotropy MTJ is deposited above a heavy metal layer with a tilted long-axis. The elliptical shape induces an in-plane anisotropy field, which is combined with the tilted layout to break the symmetry. Therefore the MTJ could be deterministically switched to high or low resistance state by applying a current along AP-path or P-path. Furthermore, the switching operation is only dependent on the current path, regardless of the current direction. This feature makes it possible to design novel high-performance MRAM.

In this paper, we design an erasable spintronics memory based on the SOT-MTJ shown in Fig. 1 (briefly called current-path-dependent SOT-MTJ in the following texts). In our design, two unidirectional currents along P-path and AP-path are used to erase and program data. The erase operation could be shared by multiple bit-cells, resulting in higher storage density. Both erase and program currents are unidirectional, thus the source degradation effect of the access transistors could be avoided.^18,19 Simulation results demonstrate the proposed erasable spintronics memory improves the density, power consumption and write speed, compared with the conventional SOT-MRAMs.

It is worth noting that there are four terminals in the heavy metal layer of the current-path-dependent SOT-MTJ for providing two current paths (see Fig. 1). However, only two terminals are involved in the heavy metal layer of the conventional SOT-MTJ. Therefore it seems that more access transistors are required to efficiently control the write operation of the current-path-dependent SOT-MTJ, which incurs larger area overhead. Fortunately, the write currents are unidirectional, which allows to simplify the bit-cell design. The detailed bit-cell structure is shown in Fig. 2, where a diode (D1) replaces the MOS transistor for carrying the program current (I_Pr) in the AP path. Even though there is a voltage drop on the diode, the write operation can still work well because the program currents needed are relatively small. Similarly, the access transistor for read operation could also be replaced with a diode (D2).^20,21 The read operation could be correctly performed with two diodes respectively connected in the test branch and reference branch of the sensing amplifier. Diodes for write and read operation are both TiO_X-based Schottky diodes²² that can be fabricated above the CMOS part, which means the cell density is mainly determined by the size of the access transistors. In this way, the area overhead is significantly reduced since the diode occupies a negligible area compared with the MOS transistor. While ‘Er’ is set to high level, the current $IEr$ will pass through the P-path to implement the erase operation. ‘$VPr$’ and ‘Pr’ can make the diode D1 and the transistor M3 active for the program operation (achieved by $IPr$⁠), respectively. The read operation is performed by applying a read current (⁠$Iread$⁠) and sensing the MTJ resistance state. It is important to mention that there is no sneak current flowing through the MTJ during the erase or program operation, thanks to the reverse-biased diode.

Based on the above bit-cell structure, we design a m×n erasable spintronics memory shown in Fig. 3, where the P-paths within each row are connected together so that the erase operation are shared. With this structure, the number of the access transistors is reduced for achieving a more area-efficient design. Moreover, the cell area could be further decreased by enlarging the capacity of the memory array. The diodes at the AP-paths within one column are connected together as the source line (SL) of the memory, while the gates of transistors at the AP-paths within one column are connected together as the bit line (BL). The sources of transistors at the AP-paths within one row are connected together as the word line (WL) of the memory.

As mentioned above, the data writing is implemented through the erase operation and subsequent program operation. For the erase operation, only transistors connected to P-paths are activated (e.g. $ME0$ and $ME0′$ in the first row) for generating erase currents to switch all the MTJs to P states. Then the program operation only occurs in those columns which need to be switched to AP states. The BLs and SLs of those columns are applied to high levels, meanwhile the WL of the selected row is set to low level. As a result, only those MTJs on the cross point of the selected columns and row are switched to AP states by program currents flowing through the AP-paths. An example of the signal settings for erase and program operations are shown in Fig. 4, where the data ‘10…1’ is written into one row.

As for the read operation, we adopt a widely-used pre-charged sense amplifier (PCSA).²³ By applying the low level to a WL, read currents (⁠$Iread$⁠) from the SAs pass through the MTJs and corresponding diode/transistor, as shown in Fig. 3. The resistance states of the MTJs are translated into the output signals of the SAs.

Based on the above write/read operations, almost no sneak current exists in the proposed spintronics memory. This advantage is attributed to the well-designed signal sequences, the unipolar conductivity of diodes, and the symmetry of the circuit structure.

Using a developed Verilog-A model of current-path-dependent SOT-MTJ and CMOS 40 nm design kit, we simulate the proposed erasable spintronics memory with Spectre simulator. The write and read operations of 4×8 memory have been validated through the transient simulation, as shown in Fig. 5. The parameters for device and circuit are configured as Table I. It is seen from Fig. 5 that the switching of the MTJ could be achieved within one nanosecond, which is in agreement with the reported results.¹⁶ 

For comparison purpose, another field-free SOT-MRAM, i.e. the SOT-assisted STT-MRAM,¹¹ is also simulated using the same MTJ thermal stability barrier as our proposed memory. For the SOT-assisted STT-MRAM, the Gilbert damping constant is reduced to 0.02, and the tunneling polarization is set to 0.5. The other parameters are configured as Table I. The results of the performance comparison are shown in Table II. Correspondingly, the write energy of the SOT-assisted STT-MRAM is much higher than that of our memory. Such performance improvements could be attributed to the advanced current-path-dependent SOT switching mechanism. In particular, both the erase and program currents of our memory are unidirectional, thus the transistors do not suffer from the source degeneration effect.^17,18 In addition, some advantages of the conventional SOT-MRAM is still kept in our memory. For instance, neither erase nor program current passes through the MTJ, which benefits the endurance and reliability of the MTJ.

We have proposed an erasable spintronics memory based on a novel field-free SOT switching mechanism. The architecture of the memory array is optimized for improving the storage density. The erase and program operations could be achieved in our proposed memory at sub-nanosecond speed and femto-joule energy. Thus, the proposed erasable spintronics memory is a good candidate for the embedded applications such as upper level caches.

This work was partly supported by the National Natural Science Foundation of China under Grant 61704005. The authors acknowledge the financial support from the VR innovation platform from Qingdao Science and Technology Commission and Magnetic Sensor innovation platform from Laoshan District.