Patterning solution-processed organic single-crystal transistors with high device performance

The application of organic field-effect transistors (OFETs) in next generation electronic products has been the subject of intensive interest due to simple fabrication, low cost, and large area.^1,2 A significant number of studies in this field have considered organic single crystals (OSCs) as ideal materials for devices with the highest performance due to their highly ordered molecules. Grain boundaries and molecular disorder in amorphous or polycrystalline thin films limit the charge transport by scattering charge carriers. The absence of these scattering centers is the principal advantage of OSCs.³ The reported values of carrier mobility are over one order of magnitude higher in OSCs than those in OFETs made of polycrystalline semiconductors.^4–8 

Despite the reported high mobility of OSC transistors, numerous factors limit their application. One is the difficulty in the patterning of OSC transistors, which is beneficial for the reduction of parasitic current paths (crosstalk) between neighboring devices. In thin-film transistors, simple patterning of the active semiconductor layer is carried out via shadowmasking.^9,10 For OSCs, hand picking and placing individual crystals is the most common approach. However, this process limits the potential industrial application of OSCs and lowers device performance due to the introduction of contamination and crystal damage.^11,12 Recently, patterning of vapor-grown organic crystals by controlling the nucleation location has been reported. The field-effect mobility (μ_FET) is over 2.0 cm²/V s based on rubrene single crystals.^13–18 In comparison, device performance of solution-processed OSC transistors on patterned substrates is considerably lower.^18–21 Therefore, patterning solution-processed OSC transistors with device performance comparable to that of the vapor-sublimed devices remains a challenge.

In the present work, self-assembled monolayer (SAM) was grown on SiO₂/Si substrate and selectively exposed to UV-ozone to form patterned wettability.^22,23 The P-type organic semiconductor dioctylbenzothienobenzothiophene (C8-BTBT) was subsequently deposited from a solution mixed with polymer dielectric of polymethylmethacrylate (PMMA). The patterned films were treated with solvent-vapor annealing (SVA) under ambient conditions, such as exposure of the functional materials to saturated solvent vapor to allow partial dissolution and recrysallization.^24–26 The resulting transistors exhibited μ_FET of up to 3.5 cm²/V s in the saturation regime of the transfer characteristics. The devices also showed good reliability in bias-stress measurement, suggesting a low density of localized states at the active regions for the OSCs via the SVA process. Our results demonstrated an easy and efficient solution-processed method of patterning OSCs for transistors application with high device performance. Moreover, further analysis on the device performance showed that the field-effect mobility is highly dependent on contact resistance.

The molecular structures of the materials used are shown in Fig. 1(a), including (tridecafluoro-1,1,2,2-tetrahydrooctyl)trichlorosilane (FTS), PMMA, and C8-BTBT. The fabrication process for the patterned OSC transistors is illustrated in Fig. 1(b). Pre-cleaned SiO₂ (200 nm)/Si substrate was immersed overnight in the FTS solution with chloroform in a glove box with nitrogen atmosphere. The FTS lowered the surface energy of substrate dramatically and achieved a water contact angle of approximately 93°, compared to the 53° angle of the bare SiO₂/Si substrate. After cleaning by ultrasonication in chloroform, acetone, and isopropanol, the substrate with FTS was covered with a shadowmask and subjected to UV-ozone treatment for 5 min. The treatment resulted in partial removal of the hydrophobic FTS layer and formation of hydrophilic square areas (0.5×0.4 mm²) without FTS coating. Subsequently, the mixture solution of C8-BTBT (0.5 wt%) and PMMA (1 wt%) in anisole was spin-coated onto the substrate with patterned wettability. Due to the wettability difference, small droplets were confined in the square regions without FTS and formed film arrays after spin-coating, resulting in selective deposition in desired geometry. A C8-BTBT and PMMA double layer was formed due to phase separation, which conforms to the result of a previous study.²⁴ Subsequently, the as-spun film arrays with polycrystalline C8-BTBT were annealed with chloroform saturated vapor under ambient conditions at room temperature and reorganized into single crystals via self-assembly. As a critical factor in the formation of C8-BTBT crystals during the SVA process, PMMA provides a high molecular mobility to facilitate rearrangement of C8-BTBT molecules over a large distance on the substrate.²⁴ The previous study showed that resulting OSCs are located on the thin polymeric dielectric PMMA film (approximately 20 nm). Thus, an OSC/dielectrics structure can be formed spontaneously during the SVA process. This suggests that our method could be further applied in devices used for simple fabrication with lower cost. Figs. 1(c) and 1(d) shows the formation of C8-BTBT crystals within the patterned regions after the SVA process. The crystals exhibited strong birefringence under the cross-polarized microscope [Fig. 1(e)], confirming their crystalline nature. Previous studies have shown that C8-BTBT crystals are in the face-centered cubic unit cells with a growth orientation along the crystal direction [100].^24,27–29 Finally, MoO_X and Au were thermally evaporated through a shadowmask to form the source and drain electrodes. Approximately 70% of the patterns on the substrate were with the OSCs that are bridging the source and drain electrodes.

The transfer and output curves of a typical OSC transistor are shown in Figs. 2(a) and 2(b), respectively. The figure shows the negligible hysteresis in both curves. Besides, the gate leakage current is in the region of 10⁻¹⁰ to 10⁻¹³ A. The field-effect mobility (μ_FET) was extracted from the saturation regime with the capacitance of 1.5×10⁻⁸ F/cm² (20 nm PMMA on 200 nm SiO₂). The FET yielded a saturation regime mobility of 3.5 cm²/V s with an on/off ratio greater than 10⁷. The threshold voltage (V_T) and sub-threshold swing (S) were −0.6 V and 0.7 V/dec, respectively. Such a high mobility results from highly ordered semiconducting molecules in the conducting channel, allowing efficient charge transport along the crystal growth orientation. As V_T and S are determined mainly by the density and distribution of the traps in the active area, the small V_T and S indicate low trap density at the semiconductor/dielectrics interface.³⁰ Figure 2(b) shows the output characteristics of the device and reveals its good field-effect transistor behavior. Consequently, the results show that our method is an efficient approach for patterning OSC transistors with high device performance, which is comparable to the patterned transistors based on the vapor-phase deposited organic crystals, such as rubrene and pentacene. Compared with devices with OSCs obtained from the natural drying solution, the significant improvement in the performance of our device is due to the fact that the SVA process allows longer and more controllable time for reorganization and recrystallization, leading to a higher degree of molecular order.

Despite the featured high performance, the devices showed variation in μ_FET ranging from 0.2 to 3.5 cm²/V s. This variation has been reported in FETs with other OSCs and is attributed to the anisotropy of charge transport, influence of channel traps, and variation in contact resistance.^19,31 In our devices, the effect of anisotropy was less apparent because the carriers transport preferentially in the [100] crystal direction. However, the influence of channel traps as defects of C8-BTBT crystals and at the active interfaces were probably introduced during the SVA process under ambient conditions. Such intrinsic defects could trap the mobile charge carriers in the channel, shifting V_T under prolonged operation in ON condition and lowering device reliability.³¹ Thus, we carried out the bias-stress measurement in vacuum and excluded the influence of water and oxygen from ambient conditions during electrical measurement. In Fig. 3(a), a slight shift of the transfer curve to negative is observed even after application of a stress of −40 V gate voltage for 12 h, and even when the OFF current remained at a very low level. The drain current managed to keep approximately 86% of the initial value, and the shift of V_T (ΔV_T) was only −1.5 V after bias-stress measurement for 12 h [Fig. 3(b)]. As a result, μ_FET extracted from each transfer curve was maintained within a small range of magnitude [Fig. 3(b)], and remained as high as 2.6 cm²/V s after the entire bias-stress measurement. This reliability indicates that charge trapping in pre-existing or stress-generated deep localized states in OSC bulk and at the dielectric interfaces is limited despite the fabrication under ambient conditions with oxygen and water.³¹ Moreover, as reported in polycrystalline OFETs, charge trapping into the deep trap states at the grain boundary in the metal/semiconductor contact region could also bring about bias-stress instability.³² However, in our OSC transistors, the density of trap states in the contact regions was less than the organic polycrystalline surface. Moreover, the discrepancy between the initial μ_FET in the bias-stress test and that in the device performance measurement could be due to the influence of ambient environment on the top surface of organic crystals because the bias-stress test was carried out more than twenty days after the device performance was measured. However, when the device was measured several months after the bias-stress test, it still showed good device performance with the extracted μ_FET close to 3 cm²/V s. It indicates that the present device exhibits long-term stability in performance after a slight degradation.

As shown above, the intrinsic defects from the SVA process and the stress-generated localized states in the channel region are limited. This suggests that the variation of field-effect mobility is highly dependent on contact resistance. To evaluate contact effects, we applied the Y function method (YFM). The method was established for silicon metal-oxide-semiconductor FETs (MOSFETs)³³ and has been applied recently in OFETs,³⁴ to estimate contact resistance and low-field mobility (μ₀) from individual devices. Contact resistance includes resistance at the metal/organic interface and access resistance from metal/semiconductor interface to the conducting channel. Moreover, μ₀ characterizes the intrinsic carrier mobility as the maximum available mobility in real transistors assuming the contact resistance is equal to zero.³⁴ 

In the YFM, the Y function is defined as:

where G_m = (W/L)μ₀C_i is the transconductance parameter. The transconductance, g_m can be written as:

where θ = θ₀+θ^* = θ₀+G_mR_sd. From equation (1) we obtain

and from equation (2)

θ₀ is related to surface roughness and phonon scattering, and its value is very small compared to the effective θ values.³⁴ Thus, contact resistance can be estimated from the slopes of the plots of Y-V_g and g_m^−1/2-V_g, when the drain voltage is low to set the device in the linear regime. In Fig. 4, the value of μ_FET (V_D=−40 V, saturation regime) is significantly lower than μ₀ in each individual device, and generally decreases with the increase in contact resistance.^23,35 As the calculated μ₀ values are at the same level, the variation of μ_FET comes mainly from contact resistance, although the channel resistance shows certain variation. The variation in the contact resistance can be due to the different OSC thicknesses influencing access resistance.²⁴ Hence, with further improvement aimed at achieving lower and more uniform contact resistance, OFETs that exhibit higher μ_FET with smaller variation can be produced.

In conclusion, we have demonstrated a method for patterning OSC transistors using surface selective deposition. The C8-BTBT OSCs were formed through SVA under ambient conditions. The devices exhibited typical transistor behavior and the highest μ_FET reached 3.5 cm²/V s. Good reliability under bias-stress measurement suggests that the density of the intrinsic defects in the crystals and the density of traps at the active interfaces are limited. Further analysis on device performance showed that μ_FET was influenced by the contact resistance. For further improvement and future application in real devices, several technical requirements, such as controllable orientation/alignment of the organic crystals in patterned areas with lower and more uniform contact resistance, are desirable. Such progress is based on a deeper understanding of the growth mechanism of OSC, of which we are currently conducting a study on.

This study is supported partially by the Grand-In-Aid for Scientific Research (No. 218505) from the Ministry of Education, Culture, Sport, Science and Technology of Japan.